Ver 1.3
PRELIMINARY
EAGLE
3.4.1 GDMA Interrupt Status Register (GDMASTAT)
The Interrupt Status Register reflects error and status of the generated interrupt.
Address : FFE0 0800h
Bit
31:18
17
R/W
R
R
Description
Default Value
Reserved
Ch1 Error Status Bit
-
0b
0 : Okay
1 : Error
16
R
Ch0 Error Status Bit
0b
0 : Okay
1 : Error
15:2
1
R
R
Reserved
-
0b
Ch1 Terminal count Interrupt Status
0 : Idle 1 : Occurred Interrupt
Ch0 Terminal count Interrupt Status
0 : Idle 1 : Occurred Interrupt
0
R
0b
3.4.2 GDMA Interrupt Mask Register (GDMAIM)
Interrupt mask Register enables and disables the interrupt signal lines.
Address : FFE0 0804h
Bit
31:18
17
R/W
R
R/W
Description
Default Value
Reserved
-
0b
Ch1 Error interrupt mask
0 : enable interrupt
Ch0 Error interrupt mask
0 : enable interrupt
Reserved
1 : disable Interrupt
1 : disable Interrupt
16
R/W
0b
15:2
1
R
R/W
-
0b
Ch1 Terminal count interrupt mask
0 : enable interrupt
1 : disable Interrupt
0
R/W
Ch0 Terminal count interrupt mask
0b
0 : enable interrupt
1 : disable Interrupt
3.4.3 GDMA Enable Status Register (GDMAESTAT)
Enable Status Register shows the enable and disable status of each channel.
Address : FFE0 0808h
Bit
31:2
1
R/W
R
R
Description
Default Value
Reserved
-
0b
Ch1 Status
0 : disable
Ch0 Status
0 : disable
1 : enable
1 : enable
0
R
0b
65
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
