Ver 1.3
PRELIMINARY
EAGLE
CONTENTS
1
DESCRIPTIONS AND FEATURES .............................................................................................................................13
1.1
1.2
GENERAL DESCRIPTION..................................................................................................................................................13
FEATURES ......................................................................................................................................................................13
2
BLOCK DIAGRAM & PIN DESCRIPTION...............................................................................................................16
2.1
2.2
2.3
2.4
BLOCK DIAGRAM ...........................................................................................................................................................16
PACKAGE DIMENSION ....................................................................................................................................................17
PIN INFORMATION ..........................................................................................................................................................19
PIN DESCRIPTION ...........................................................................................................................................................24
3
REGISTER DESCRIPTIONS........................................................................................................................................33
3.1
SYSTEM..........................................................................................................................................................................44
3.1.1
3.1.2
3.1.3
3.2
System ID Register (SYSID)...................................................................................................................................44
Configuration Register (CFG)...............................................................................................................................44
USB Host/Device Select Register (USBSEL).........................................................................................................44
PIN MUX ........................................................................................................................................................................45
Pin Mux Control Register 0 (PINMUX0) ..............................................................................................................45
Pin Mux Control Register 1 (PINMUX1) ..............................................................................................................46
Pin Mux Control Register 2 (PINMUX2) ..............................................................................................................46
Pin Mux Control Register 3 (PINMUX3) ..............................................................................................................47
Pin Mux Control Register 4 (PINMUX4) ..............................................................................................................48
Pin Mux Control Register 5 (PINMUX5) ..............................................................................................................49
Pin Mux Control Register 6 (PINMUX6) ..............................................................................................................50
Pin Mux Control Register 7 (PINMUX7) ..............................................................................................................50
LOCAL/FRAME & TEXTURE MEMORY CONTROL REGISTERS .........................................................................................51
Local Memory Bank Control Register (MEMCONn) ............................................................................................51
Local SDRAM Clock Delay & Refresh Control (MEMCLKCON) ........................................................................55
Frame Memory Area Start Address (FMASA).......................................................................................................56
1 MHz Frequency Generation Register (1MFREQGEN)......................................................................................56
Texture Memory Control Register (TMEMCON)..................................................................................................57
Texture SDRAM Clock Delay & Refresh Control (TMEMCLKCON)...................................................................57
Texture Memory Area Start Address (TMASA) .....................................................................................................58
GENERAL DMA .............................................................................................................................................................59
GDMA Interrupt Status Register (GDMASTAT) ...................................................................................................65
GDMA Interrupt Mask Register (GDMAIM).........................................................................................................65
GDMA Enable Status Register (GDMAESTAT)....................................................................................................65
GDMA Request Status & Synchronization Register (GDMARSS).........................................................................66
GDMA Configuration Register (GDMACFG).......................................................................................................67
GDMA Last Request Register (GDMALR) ............................................................................................................67
GDMA Control Register (GDMACONn)...............................................................................................................68
GDMA Source Address Register (GDMASn) ........................................................................................................69
GDMA Destination Address Register (GDMADn)................................................................................................69
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.8
3.4.9
3.4.10 GDMA Transfer Count Register (GDMATn).........................................................................................................69
3.4.11 GDMA Descriptor Table Address Register (GDMADTn).....................................................................................69
3.5
INTERRUPT CONTROLLER...............................................................................................................................................70
External Interrupt Source Select & Interrupt Mode Register (INTMOD).............................................................71
Interrupt Vector Register (INTVEC)......................................................................................................................72
Interrupt Vector Clear Register (INTVECCLR) ....................................................................................................72
Interrupt Enable Register (INTEN) .......................................................................................................................73
Interrupt Status Register (INTSTAT).....................................................................................................................74
Interrupt Priority Programmable Register (INPPRn)...........................................................................................75
Interrupt Trigger Mode Programmable Register (IRQTRMD) .............................................................................76
Interrupt Output Masking Register (INTMSK)......................................................................................................77
MCU Core Handshake Register (INTHSMCU).....................................................................................................77
NAND FLASH CONTROLLER..........................................................................................................................................78
NAND Flash Memory Control Register (NFMCON) ............................................................................................81
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
3.6
3.6.1
3
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
