Ver 1.3
PRELIMINARY
EAGLE
3.31.2 System Coprocessor Register
Registers
R0
Attr.
Descriptions
Remarks
R/W OSI Control / Status / Data Register (DIX 00 – 08)
R/W OSI Index Register
R/W OSI RS-232C Tx/Rx Data Register
R/W General Access Point Index Register
R/W General Access Point Data Register
R/W Sub-bank Address Register
R1
R2
R3
R4
R5
R/W TLB Virtual Address Register
R/W TLB Physical Address Register
R/W TLB Index Register
R6
R7
R8
R9
R/W Sub-bank Index / Configuration Register
R/W Memory Bank Register
R10
R11
R12
R13
R14
-
W
-
Reserved
Invalidate Cache Register
R/W Vector Base Register
R/W User Stack Pointer
R/W Supervisor / OSI Stack Pointer
W
R
Master Command Register
Status Register
R15
3.31.2.1 Status Register(Read Only)
Co-processor #0 – R15
Default
Value
1b
001b
000b
Bit
R/W
Description
31
30:28
27:25
R
R
R
System Co-processor (Privileged)
Type
Subtype
Download Channel
00 : No Shared Channel
01 : Parallel Port
10 : USB
11 : Ethernet
OSI configuration
00 : No OSI
01 : 2 channel OSI.
10 : 4 channel OSI.
11 : 8 channel OSI.
24:23
22:21
20:19
R
R
R
00b
11b
01b
TLB configuration
00 : No TLB
01 : Unified, 4-way, 128 Entry TLB
10 : Separated, I : 4way, 64entry D: 4way, 64entry
10 : Separated, I : 4way, 128entry D: 4way, 128entry
L1 Cache Configuration
0 : L1 Cache Present
1 : L1 Cache Not Present (invalid pre-fetch)
L1 Cache Configuration - Snooping
L1 Cache Configuration – Write Policy
0 : write-through
18
17
R
R
R
R
0b
0b
0b
-
16
1 : write-back
Reserved
15 : 10
OSI Break Cause
00 : OSI Instruction Break
01 : OSI Data Break
9:8
R
00b
10 : OSI Packet Receive (full)
221
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
