Ver 1.3
PRELIMINARY
EAGLE
3.31.2.3 Supervisor/OSI Stack Pointer Register
Co-Processor #0 – R14
Bit
R/W
Description
Default Value
Supervisor stack pointer at OSI mode
OSI stack pointer at supervisor mode
Always 0
31:2
1:0
R
R
All 0’s
3.31.2.4 User Stack Pointer Register
Co-processor #0 – R13
Bit
R/W
Description
Default Value
31:2
1:0
R
R
User stack pointer
Always 0
All 0’s
3.31.2.5 Vector Base Register
Co-processor #0 – R12
Bit
R/W
Description
Exception vector table virtual address bit
Always 0
Default Value
31:2
1:0
R
R
All 0’s
3.31.2.6 Cache Invalidation Register
Co-processor #0 – R11
Bit
31:7
6:4
R/W
W
W
Description
Default Value
All 0’s
Target Address
Target Address / Target Way
0b
Operation
3
W
0 : Address based invalidation
1 : Way based invalidation
write-back enable/disable
0 : w/o write-back
1 : w/ write-back if needed , supported in address based invalidation.
Reserved
Cache Type
0 : Instruction cache
1 : Data cache
0b
2
1
0
W
W
W
0b
0b
0b
3.31.2.7 Memory Bank Register
Co-processor #0 – R9
Bit
R/W
Description
Default Value
Memory Bank 7 configuration
Memory Bank 7 TLB address translation
0 : Disable TLB
31:28
R/W
0000b
31
1 : Enable TLB
223
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
