EAGLE
PRELIMINARY
Ver 1.3
Memory Bank 7 access right (TLB disable)
0 : Supervisor only access
1 : User / Supervisor access
Memory Bank 7 TLB Page size (TLB enable)
0 : 4KB
30
1 : 256KB
Memory Bank 7 cache configuration (Valid only if TLB is disabled)
00 : Disable cache, disable write buffer
29:28 01 : Disable cache, enable write buffer
10 : Write through cache, enable write buffer
11 : Write back cache, enable writ buffer
27:24
R/W Memory Bank 6 configuration
0000b
23:20
19:16
15:12
11:8
7:4
R/W Memory Bank 5 configuration
R/W Memory Bank 4 configuration
R/W Memory Bank 3 configuration
R/W Memory Bank 2 configuration
R/W Memory Bank 1 configuration
R/W Memory Bank 0 configuration
0000b
0000b
0000b
0000b
0000b
0000b
3:0
3.31.2.8 Sub-bank Index/Configuration Register
Co-processor #0 – R8
Bit
R/W
Description
Default Value
31 : 7
R
Reserved
-
Sub-bank Index Register
000 : Sub-bank0
001 : Sub-bank1
010 : Sub-bank2
6:4
R/W 011 : Sub-bank3
100 : Sub-bank4
00b
101 : Sub-bank5
110 : Sub-bank6
111 : Sub-bank7
Sub-bank Configuration (indexed by Bit[6:4])
bit 3 : configuration information validity
0 : invalid, 1 : valid
bit 2 : Access right
0 : Supervisor only access, 1 : User/Supervisor access
bit [1:0] : Cache Disable
3:0
R/W
0000b
00 : Disable cache, disable write buffer
01 : Disable cache, enable write buffer
10 : Write through cache, enable write buffer
11 : Write back cache, enable writ buffer
3.31.2.9 TLB Index Register
Co-processor #0 – R7
Bit
31:8
7
R/W
Description
Default Value
R/W Reserved
R/W TLB select
All 0’s
0 : Select instruction fetch TLB
1 : Select data access TLB
R/W TLB index
TLB index = VA16-VA12/PA11-PA0=VA11-VA0
R/W TLB set
6:3
2:1
All 0’s
All 0’s
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
224
ETC [ ETC ]
