Ver 1.3
PRELIMINARY
EAGLE
3.29.13 JPEG DECODER STATUS Register (JDSTAT)
Address : FFE1 8000h
Bit
31 : 4
R/W
R
Description
Default Value
Reserved
-
3
2
1
0
R
R
R
R
JPEG Decoder Finished
JPEG Decoder MCU Decoding
JPEG Decoder Header Parsing
JPEG Decoder Ready
0b
0b
0b
0b
3.29.14 JPEG DECODER IRQ STATUS Register (JDIRQSTAT)
Address : FFE1 8004h
Bit
31 : 2
1
R/W
R
R
Description
Default Value
Reserved.
-
0b
JPEG Decoder FIFO Fill Request IRQ
Interrupt is triggered when the compressed data in JPEG Decoder
Internal FIFO is not filled up to the level configured in JDCTRL
Register [6:0].
0
R
JPEG Decoder End IRQ
0b
Display the end point of JEPG Decoder. after JPEG Decoder decodes
the required number of MCU in decoder, this IRQ shall occur when
JPEG EOF Flag is arrives in Decoder.
*this interrupt is inputted to JPEG image capturer and used for the
source of JICIRQ.
3.29.15 JPEG DECODER Data FIFO Status Register (JDDFSTAT)
Address : FFE1 8008h
Bit
31 : 7
6 : 0
R/W
R
R
Description
Default Value
Reserved.
Current FIFO Level Status
-
00h
Show current input data FIFO level.
When input data is written into the FIFO, input data must be written
within the value of Current FIFO Level Status of under 3Fh. If
exceeded, new subsequent data will overwrite the existing data in
FIFO.
3.29.16 JPEG DECODER Enable Register (JDENA)
Address : FFE1 8010h
Bit
31 : 1
0
R/W
R
R/W
Description
Default Value
Reserved.
JPEG Decoder Enable
-
0b
This bit enables JPEG decoder. After this bit is set to 1, JPEG
Decoder shall start data decoding when bit 0 of JDCOMCON register
is set to ‘1’.
3.29.17 JPEG DECODER FIFO Clear Register (JDFCLR)
Address : FFE1 8014h
Bit
31 : 4
3
R/W
R
R/W
Description
Default Value
Reserved.
-
0b
FIFO Clear
1:ALL FIFO Clear
0:IDLE
2 : 0
R
Reserved
-
217
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
