欢迎访问ic37.com |
会员登录 免费注册
发布采购

PKM32AG-Q 参数 Datasheet PDF下载

PKM32AG-Q图片预览
型号: PKM32AG-Q
PDF下载: 下载PDF文件 查看货源
内容描述: EAGLE是一款多媒体处理器.EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。 [EAGLE是一款多媒体处理器。EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。]
分类和应用: 解码器编码器控制器
文件页数/大小: 235 页 / 4257 K
品牌: ETC [ ETC ]
 浏览型号PKM32AG-Q的Datasheet PDF文件第211页浏览型号PKM32AG-Q的Datasheet PDF文件第212页浏览型号PKM32AG-Q的Datasheet PDF文件第213页浏览型号PKM32AG-Q的Datasheet PDF文件第214页浏览型号PKM32AG-Q的Datasheet PDF文件第216页浏览型号PKM32AG-Q的Datasheet PDF文件第217页浏览型号PKM32AG-Q的Datasheet PDF文件第218页浏览型号PKM32AG-Q的Datasheet PDF文件第219页  
Ver 1.3  
PRELIMINARY  
EAGLE  
3.29.1 JPEG DECODER MCU WIDTH Register (JDMWIDTH)  
Address : FFE1 0234h  
Bit  
31 : 12  
11 : 0  
R/W  
R
W
Description  
Default Value  
Reserved.  
-
0h  
JPEG Decoder MCU WIDTH  
Set MCU width for image decoding.  
*MCU WIDTH = Image Width/16  
(input image width for JPEG decoder must be multiple of 32)  
3.29.2 JPEG DECODER MCU HEIGHT Register (JDMHEIGHT)  
Address : FFE1 0238h  
Bit  
31 : 12  
11 : 0  
R/W  
R
W
Description  
Default Value  
Reserved.  
-
0h  
JPEG Decoder MCU HEIGHT  
Set MCU height for image decoding.  
*MCU HEIGHT = Image Height/16( YCBCR 420 Format)  
*MCU HEIGHT = Image Height/8 ( YCBCR 422 Format)  
(Input image height for JPEG decoder must be multiple of 16 for 420  
format or multiple of 8 for 422 format)  
3.29.3 JPEG DECODER Quantization Scale Control Register (JDQSC)  
Address : FFE1 023Ch  
Bit  
31 : 12  
11 : 0  
R/W  
R
W
Description  
Default Value  
Reserved.  
-
0h  
JPEG Quantization Scale Control  
Scale quantization table value in the JPEG image header. With 64 as  
base value, larger number increases Q table value and smaller number  
decreases Q table value  
If other value other than 64 is used, image distortion may occur under  
the condition of different value setting.  
3.29.4 JPEG DECODER Command Control Register (JDCOMCON)  
Address : FFE1 0240h  
Bit  
31 : 3  
2
R/W  
R
W
Description  
Default Value  
Reserved.  
-
0b  
JPEG Decoder End IRQ Clear  
1:End IRQ Clear  
0:IDLE  
JPEG Decoder End IRQ is used as JICIRQ source. This bit is set  
when both JPEG Decoder End IRQ and JICIRQ are cleared.  
After changing to ‘1’, this bit will toggle back to ‘0’ at the next clock.  
After this bit is set to ‘1’, it is automatically cleared to ‘0’ at the next  
clock.  
*JPEG Decoder End IRQ must be cleared for JPEG decoder to  
decode the next image  
1
0
W
W
DECODING IMAGE FORMAT  
1:YCBCR 420  
0:YCBCR 422  
Decoding Start  
0b  
0b  
1:Decoding Start  
0:IDLE  
If JDENA Register[0] is set to ‘1’, JPEG decoder shall operate when  
this bit changes to ‘1’.  
The first JPEG Decoder FIFO Fill Request IRQ is initiated by setting  
this bit to ‘1’.  
After decoder starts the decoding operation, this bit will be cleared  
automatically.  
215  
CONFIDENTIAL  
Beijing Peak Microtech Co.Ltd.  
 复制成功!