Ver 1.3
PRELIMINARY
EAGLE
3.28.5 SCK Phase and Polarity Control
SPI in eagle can determine the SCK polarity and phase. The CPOL bit selects the polarity of SCK while CPHA bit selects
the phase of SCK which influences the transfer timing. In General, the Master SCK polarity and phase must be same as slave
SCK polarity and phase. But In some cases, Master and slave may transfer data under a different condition. The flexibility of
SPI allows communication with almost all synchronized serial devices.
SSX
SCK
(CPOL=0, CPHA=0)
SCK
SCK
SCK
(CPOL=0, CPHA=1)
(CPOL=1, CPHA=0)
(CPOL=1, CPHA=1)
MSB
1
2
3
4
5
6
LSB
MSB if CPHA=0
Internal strobe for data capture (for all modes)
Figure 3-57 SCK Phase and Polarity
3.28.6 Data Transfer Timing
The following figure describes the data timing in Master mode. The same applies to Slave mode.
In the case of CPHA=0, data sampling occurs for one clock cycle when clock phase is 0, and next data is sent out when
clock phase is 180
SCK CYCLE
1
2
3
4
5
6
7
8
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(Master Out)
MSB
6
6
5
4
3
2
2
1
LSB
LSB
MISO
(Master In)
MSB
5
4
3
1
SSX
(To Slave)
Figure 3-58 Transfer Timing when CPHA = ‘0’
207
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
