Ver 1.3
PRELIMINARY
EAGLE
3.28.7.2 SPI Baud Rate Register (SPIBR)
Address : 0xFFE0_B004h
Bit
31 : 8
7 : 0
R/W
R
R/W
Description
Default Value
Reserved.
Serial Clock Baud Rate
-
FFh
fAPB _ Clock
fSCK
=
2× (SPIBRR [7 : 0]+1)
Master Mode SCK ≤APB Clock / 2
Slave Mode SCK ≤APB Clock / 8
The Baud rate ranges from 0 to 255. When SPI operates in slave mode, SPIBR has no effect. But the SCK Frequency which
can be accepted by Slave SPI is 1/8 times lower than the APB clock frequency.
3.28.7.3 SPI Status Register (SPISTAT)
Address : 0xFFE0_B008h
Bit
15 : 8
7
R/W
R
R
Description
Default Value
Reserved
-
0b
SPIF : SPI Finished Flag
0 : SPI is not finished.
1 : SPI is finished.
WCOL : Write Collision
0 : No error
6
5
R
R
0b
0b
1 : when FIFO is full and attempt to write new data in FIFO sets
WCOL.
MODF : Mode Fault Flag
0 : No error
1 : MODF is set when multi SPI master attempts to access SPI
slave simultaneously.
4
3
2
1
0
R
R
R
R
R
SSX : Slave Select Flag
0b
0b
0b
0b
0b
0 : Current value of SSX port is low
1 : Current value of SSX port is high
STXF : TX FIFO Full Status bit
0 : FIFO_TX is not full
1 : FIFO_TX is full
STXE : TX FIFO Empty Status bit
0 : FIFO_TX is not empty
1 : FIFO_TX is empty
SRXF : RX FIFO Full Status bit
0 : FIFO_TX is not full
1 : FIFO_TX is full
SRXE : RX FIFO Empty Status bit
0 : FIFO_RX is not empty
1 : FIFO_RX is empty
209
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
