Ver 1.3
PRELIMINARY
EAGLE
3.28.7.7 SPI Transfer Mode Register (SPITM)
Address : 0xFFE0_B018h
Bit
31 : 15
14 : 4
3
R/W
R
R/W
R/W
Description
Default Value
Reserved.
-
Number of data transferred by DMA in bytes.
000h
0b
DMA on / off bit
0 : DMA Off
1 : DMA On
2
1
0
R/W
R/W
R
TX mode
0b
0b
-
0 : SPI Operation is Full duplex
1 : Tx data is transmitted but Rx data is not stored.
RX mode
0 : SPI Operation is Full duplex
1 : Rx data is received but Tx data stays high.
Reserved
3.28.7.8 SPI Clock Select Register (SPICS)
Address : 0xFFE0_B01Ch
Bit
31 : 1
0
R/W
R
R/W
Description
Default Value
Reserved
SCK clock select bit
-
0b
0 : SCK is system clock divided
1 : SCK is external clock divided
3.28.7.9 SPI Response Character Register (SPIRC)
Address : 0xFFE0_B020h
Bit
31 : 9
8
R/W
R
R/W
Description
Default Value
Reserved.
-
0b
Response character exclusive
0 : keep sending data until response character arrive.
1 : keep sending data until any data which is different from response
character arrive
7 : 0
R/W
Response character
00h
This is a special function where user may only use this function in RX mode with DMA off and SPI in Master mode. This
function helps user to filter out unnecessary data and receive only necessary data in RX FIFO. For example, when you write
FEh in SPIRC, SPI Master shall continue to send FFh on MOSI line until FEh has arrived at MISO.
211
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
