EAGLE
PRELIMINARY
Ver 1.3
3.28.3 SPI Pins
The Function of SPI pin is determined by WOMP and MSTR bits in Control register. If WOMP bit is set, the output state
of SPI pin is open drain. If WOMP is cleared, the output state of SPI pin is CMOS output. Table 3-31 shows the function of
SPI pin
Pin Name
Master in, slave out(MISO)
Mode
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Function
Provides serial data input to the SPI
Provides serial data output from the SPI
Provides serial output from the SPI
Provides serial input to the SPI
Provides clock output from the SPI
Provides clock input to the SPI
Output : Selects slave devices
Input : chip select for SPI
Master out, slave in (MOSI)
serial clock(SCK)
Slave select(SSX)
Table 3-31 SPI Pin Functions
3.28.4 SPI Operating Modes
SPI operates in Master mode or Slave mode. Master mode is used to control data transaction and slave mode is used for
data transaction by external devices. MSTR bit in Control register determines the selection of Master mode or Slave mode.
3.28.4.1 Master Mode
When you set the MSTR bit in SPICON register, SPI operates in Master mode. Only a Master may initiate data
transactions and does not respond to the initializing transaction of other devices.
When you use master mode, you must do followings
1. External pins are shared with other functional pins in PinMux register. PinMux register must be configured to use
SPI.
2. Set Control register to configure the communication mode ( BAUD, CPHA, CPOL, SIZE, LSBF, WOMP) and
MSTR, SPIEN must be set.
3. Enable slave device by setting SSX low.
4. Write the data to be sent.
When SPI transfer completes, SPIF in Status register is automatically set. and interrupt shall occur ff Interrupt is enabled.
SPIF is automatically cleared when user reads to the Status register or Write/Read Data register.
3.28.4.2 Slave Mode
If MSTR bit is cleared, SPI operates in slave mode. Slave SPI can not initiate transactions. Slave SPI is able to send data
when SPI master sends data.
Follow the steps below when slave mode is used.
1. External pins are shared with other functional pins in PinMux register. PinMux register must be configured to use
SPI.
2. Set Control register to configure the communication mode ( BAUD, CPHA, CPOL, SIZE, LSBF, WOMP) and
SPIEN must be set and MSTR must be cleared. (In slave mode BAUD value has no effect on operation)
3. Write the data to be sent.
In Slave mode, when SSX pin status is low, device shall prepare for data transaction. When Master starts the SCK toggling,
device starts the data transaction synchronized to SCK. Completion of data transaction is noticed by checking SPIF. The
same applies to Master mode.
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