EAGLE
PRELIMINARY
Ver 1.3
For the case of CPHA=1, data is sent out when clock phase is 0 and data sampling occurs when clock phase is 180
SCK CYCLE
1
2
3
4
5
6
7
8
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MSB
MSB
6
6
5
4
4
3
3
2
2
1
1
LSB
5
MISO
SSX
LSB
Figure 3-59 Transfer Timing when CPHA = ‘1’
3.28.7 SPI Register Description
3.28.7.1 SPI Control Register (SPICON)
Address : 0xFFE0_B000h
Bit
31 : 8
7
R/W
R
R/W
Description
Default Value
Reserved
-
0b
SPIEN : SPI Enable
0 : SPI is disabled.
1 : SPI is enabled
6
5
4
3
R/W
R/W
R/W
R/W
WOMP : Wired-OR Mode for SPI Pins
0 : Outputs have normal CMOS drivers.
1 : Open-drain drivers
MSTR : Master/Slave Mode Select
0 : SPI is a slave device
1 : SPI is a system master
CPOL : Clock Polarity
0 : The inactive state of SCK is logic level zero
1 : The inactive state of SCK is logic level one.
CPHA : Clock Phase
0b
0b
0b
0b
0 : Data is captured on the leading edge of SCK and changed on
the trailing edge of SCK.
1 : Data is changed on the leading edge of SCK and captured on
the trailing edge of SCK.
2
R/W
R/W
LSBF : Least Significant Bit First
0 : Serial data transfer starts with LSB.
1 : Serial data transfer starts with MSB.
SPISIZE : Transfer Data Size
0b
1 : 0
00b
00 : 8-bit data transfer.
01 : 16-bit data transfer.
10 : 32-bit data transfer.
Open-Drain Outputs
Open-drain driver is used to avoid the bus collision in a multi SPI master system by adding pull up resistance on data line.
If only single SPI master is used, it is not necessary to use open-drain driver
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
208
ETC [ ETC ]
