EAGLE
PRELIMINARY
Ver 1.3
3.28.7.4 SPI Data Register (SPID)
Address : 0xFFE0_B00Ch
Bit
R/W
Description
Default Value
31 : 0
R/W
SPI Data
At 32-bit transfer mode
0000 0000h
- MSB of data is SPID[31]
At 16-bit transfer mode
- MSB of data is SPID[15]
At 8-bit transfer mode
- MSB of data is SPID[7]
LSB of Data (received or transmit) is SPID[0] in any transfer mode
3.28.7.5 SPI SSX Control Register (SPISCON)
Address : 0xFFE0_B010h
Bit
31 : 1
0
R/W
R
R/W
Description
Reserved
SSXCON : SSX output Level
Default Value
-
1b
3.28.7.6 SPI Interrupt Mask Register (SPIIM)
Address : 0xFFE0_B014h
Bit
31 : 8
7
R/W
R
R/W
Description
Default Value
Reserved
-
0b
SPIFE : SPIF Interrupt en/disable
SPIF Interrupt occurs when transfer has completed.
0 : SPIF interrupt is disabled
1 : SPIF is enabled
6
R/W
MODFE : MODFI Interrupt en/disable
MODFI Interrupt occurs when two or more master use data line.
0 : MODFI interrupt is disabled
0b
1 : MODFI is enabled
5
4
R
R/W
Reserved
SSXE : SSX Interrupt en/disable
-
0b
SSX Interrupt occurs when SSX signal is changed.
0 : SSX Interrupt is disabled
1 : SSX Interrupt is enabled
3
2
1
0
R/W
R/W
R/W
R/W
STXFE : FIFO_TX_FULL Interrupt en/disable
FIFO_TX_FULL interrupt occurs when FIFO_TX is full
0 : FIFO_TX_FULL interrupt is disabled
1 : FIFO_TX_FULL interrupt is enabled
STXEE : FIFO_TX_EMPTY Interrupt en/disable
FIFO_TX_EMPTY interrupt occurs when FIFO_TX is empty
0 : FIFO_TX_EMPTY interrupt is disabled
1 : FIFO_TX_EMPTY interrupt is enabled
SRXFE : FIFO_RX_FULL Interrupt en/disable
FIFO_RX_FULL interrupt occurs when FIFO_RX is full
0 : FIFO_RX_FULL interrupt is disabled
1 : FIFO_RX_FULL interrupt is enabled
SRXEE : FIFO_RX_EMPTY Interrupt en/disable
FIFO_RX_EMPTY interrupt occurs when FIFO_RX is empty
0 : FIFO_RX_EMPTY interrupt is disabled
1 : FIFO_RX_EMPTY interrupt is enabled
0b
0b
0b
0b
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
210
ETC [ ETC ]
