Ver 1.3
PRELIMINARY
EAGLE
3.27.10.2 TWI Status Register (TWISTAT)
Address : FFE0 AC04h
Bit
31 : 10
9
R/W
R
R/W
Description
Default Value
Reserved.
-
1b
TXEMPTY : TX buffer empty bit.
This bit represents TX buffer status. User may write to buffer when this
bit is 0.
1: TX buffer is empty.
0: Data to transmit exists in TX buffer.
8
7
R/W
R
RXFULL : RX buffer full bit.
This bit represents RX buffer status. User may read when this bit is 1.
1: Data to read in RX buffer.
0: RX buffer is empty.
TCF : Data Transfer complete bit
0b
0b
This bit is set whenever one byte transfer completes. This bit is cleared by
reading or writing TWIDATA or by writing a ‘1’ to this bit.
1: One byte data transfer complete.
0: Data transferring.
6
5
R
AAS : Addressed as Slave Bit.
0b
0b
When the address on TWI bus matches the Slave address in TWIADDR
register, the TWI controller acts as a Slave. This bit is cleared by writing
to TWICON or a STOP condition occurs.
1: Address matched..
0: No matched address.
BSY : Bus Busy Bit.
R/W
This bit indicates the status of TWI bus. This bit is set when a START
condition is detected and cleared when a STOP condition is detected or
by writing a ‘0’ to this bit.
1: bus is busy
0: bus is idle
4
3
R/W
R
LST : Lost Arbitration Bit.
0b
0b
This bit is set by hardware when arbitration for TWI bus is lost. MCU
clears this bit by writing a ‘0’ to this bit.
1: lost arbitration is occurred
0: lost arbitration is not occurred (cleared by the software)
SRW : Slave Read/Write Bit.
When the TWI controller is addressed as a Slave (AAS is set), this bit
indicates the value of the read/write bit sent by Master. This bit is only
valid when a complete transfer has occurred and no other transfer was
initiated.
1: Slave transmit mode
0: Slave receive mode
2
1
R
R/W
Reserved
RSF : Repeated Start flag bit
-
0b
This flag bit is used to confirm the occurrence of repeated Start condition.
This bit is set when repeated Start condition occurs and cleared by Stop
condition or by writing a 1 to this bit.
1: Repeated Start condition occurred.
0: Repeated Start condition did not occur or Stop condition occurred.
0
R
RXAK : Received Acknowledge Bit.
1b
This bit reflects the value of SDA signal during the acknowledge cycle of
data transfer.
1: Receive No Acknowledge
0: Receive Acknowledge
203
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
