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PKM32AG-Q 参数 Datasheet PDF下载

PKM32AG-Q图片预览
型号: PKM32AG-Q
PDF下载: 下载PDF文件 查看货源
内容描述: EAGLE是一款多媒体处理器.EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。 [EAGLE是一款多媒体处理器。EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。]
分类和应用: 解码器编码器控制器
文件页数/大小: 235 页 / 4257 K
品牌: ETC [ ETC ]
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EAGLE  
PRELIMINARY  
Ver 1.3  
3.27.10 TWI Registers  
3.27.10.1 TWI Control Register (TWICON)  
Address : FFE0 AC00h  
Bit  
31 : 8  
7
R/W  
R
R/W  
Description  
Default Value  
Reserved.  
-
0b  
TWIEN : TWI Controller Enable bit.  
TWI Controller Enable. This bit must be set before setting other control  
register bits that may affect the TWI operation.  
1: TWI Controller Enable  
0: TWI Controller Disable  
6
5
R
R/W  
Reserved.  
MSTA : Master/Slave Mode Select bit.  
-
0b  
When AE32000C changes this bit from ‘0’ to ‘1’, the TWI controller  
generates a START condition in Master mode. When this bit is cleared, a  
STOP condition is generated and the TWI controller switches to Slave  
mode. If this bit is cleared, due to lost of bus control resulting from bus  
arbitration, a STOP condition will not be generated.  
1 : Generate Start condition  
0 : Generate Stop condition  
4
3
R/W  
R/W  
TWITR : Transmit/Receive Mode Select bit.  
This bit selects the direction of Master data transfers. Available only in  
master device.  
1: TWI Master Transmit  
0: TWI Master Receive  
TXAK : Transmit Acknowledge Enable.  
This bit specifies the value driven onto the SDA line during the  
acknowledge cycles for both Master and Slave receivers  
Since Master receivers indicate the end of data reception by not  
acknowledging the last byte of transfer, this bit is a mean for AE32000C  
to end a Master receiver transfer.  
0b  
0b  
1: ACK bit = ‘1’ - no acknowledge  
0: ACK bit = ‘0’ – acknowledge  
2
R/W  
REPST : Repeated Start Enable.  
0b  
Writing a ‘1’ to this bit generates a repeated START condition on the bus  
if TWI controller is the current bus Master. This bit is cleared after Start  
condition is generated. This bit is always read as ‘0’.  
1: Generate Repeated Start condition  
0 : N/A  
1
0
R/W  
R/W  
TCFIRQ : Transfer complete IRQ Enable  
This bit initiates the interrupt request for one byte of data transfer.  
1 : Interrupt enable  
0 : Interrupt disable  
LSTIRQ : Lost Arbitration IRQ Enable  
0b  
0b  
This bit enables interrupt request generation for a master which lost  
arbitration.  
1 : Interrupt enable  
0 : Interrupt disable  
Beijing Peak Microtech Co.Ltd.  
CONFIDENTIAL  
202  
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