Ver 1.3
PRELIMINARY
EAGLE
3.21.3 Register Map
3.21.3.1 I2S Control Register (I2SCON)
This register defines the mode of operation of I2S.
Address: FFE0 9400h
Bit
R/W
Description
Default Value
31 : 8
7
R
R/W
Reserved
-
0b
Transmit access mode
0 : Normal / Interrupt
1 : DMA
6
5
4
3
R/W
R/W
R/W
R/W
Receive access mode
0 : Normal / Interrupt
1 : DMA
Transmit interrupt active
0 : Disable
1 : Enable
Receive interrupt active
0 : Disable
0b
0b
0b
0b
1 : Enable
Transmit pause active
0 : Disable
1 : Enable
2 : 1
0
R
Reserved
-
R/W
I2S Enable / Disable
0 : Disable ( Stop )
1 : Enable ( Start )
0b
The Transmit / Receive access mode selection bit sets the data access method.
The Transmit / Receive access mode controls whether Transmit / Receive interrupt active signal is asserted as
Interrupt enable signal or DMA request enable signal.
The Transmit pause active bit is used to activate the transmission pause operation. When this bit is set, it prevents
read/write operation to FIFO.
I2S Enable / Disable bit starts and halts the operation of I2S.
3.21.3.2 I2S Mode Register (I2SMOD)
This register sets the I2S mode.
Address: FFE0 9404h
Bit
31 : 14
13
R/W
R
R/W
Description
Default Value
Reserved
-
0b
Endian (for 32-bit)
0 : Little Endian
1 : Big Endian
Endian (for 16-bit)
0 : Little Endian
1 : Big Endian
12
11
R/W
R/W
0b
0b
Active level of left / right channel
0 : High for left channel ( Low for right channel )
1 : Low for left channel ( High for right channel )
Reserved
10
9 : 8
R/W
R/W
-
0h
Transfer mode(FIFO enable)
00 : No transfer (Tx, Rx – Off)
01 : Receive (Tx – Off, Rx – On)
10 : Transmit (Tx – On, Rx – Off)
169
CONFIDENTIAL
Beijing Peak Microtech Co.Ltd.
ETC [ ETC ]
