EAGLE
PRELIMINARY
11 : Transmit and receive (Tx, Rx – On)
Ver 1.3
7 : 6
R/W
R/W
R/W
R/W
R/W
Quantization mode
00 : Not used
10 : 8-bit linear PCM 11 : 16-bit linear PCM
Stereo mode
0 : Mono
1 : Stereo
Serial interface format
0 : I2S-bus format
1 : MSB(Left)-justified format
Master clock frequency
00 : 256fs
10 : 512fs
Serial bit clock frequency
0h
0b
0b
0h
0h
01 : 4-bit ADPCM
5
4
3 : 2
1 : 0
01 : 384fs
11 : Not used
00 : 16fs
10 : 48fs
01 : 32fs
11 : 64fs
The Endian bits configures the Byte-Swap for 32 bits or 16 bits when AE32000C core performs read or write
operation to I2SDATA registers.
The Active level of left / right channel bit decides the ‘High’ or ‘Low’ for the Left / Right channel pair. By Default,
Left channel is configured as ‘High’.
The Transfer mode bit sets the transmission / reception operation for I2S. If both transmit and receive are set as
“OFF”, the corresponding FIFO is cleared.
The Quantization mode bit decides the quantization of transmit and receive data.
The Stereo mode bit selects the mono or stereo format for transmit / receive data.
The Serial interface format, Master clock frequency and Serial bit clock frequency bits configures clock and data for
Transmission / Reception operation.
3.21.3.3 I2S Pre-scaler Register (I2SPS)
This register sets the Pre-Scaler Value of I2S.
Address: FFE0 9408h
Bit
31 : 5
4
R/W
R
R/W
Description
Default Value
Reserved
Master clock select
-
0b
Selects the source clock to generate the master clock
0 : Source Clock is APB clock
1 : Source Clock is External codec clock
3 : 0
R/W
Division Factor : 0 ~ 15
0h
Generate master clock
master clock = APB clock / ( division factor + 1 )
The Master clock select bit decides the Master clock source from APB clock or external clock
The division factor bit is used when clock source is from APB clock. When this bit is set the ‘1’, the internal Master
clock triggers the operation of external CODEC clock.
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CONFIDENTIAL
170
ETC [ ETC ]
