Ver 1.3
PRELIMINARY
EAGLE
3.21.3.4 I2S Status Register (I2SSTAT)
This register indicates the Status of I2S.
Address: FFE0 940Ch
Bit
31 : 21
20
R/W
R
R
Description
Default Value
Reserved
-
0b
Left / Right channel index (Read Only)
When Active level of left / right channel bit is ‘0’,
0 : Right
1 : Left
19
18
17
16
R
R
R
R
Transmit FIFO half level status(Read only)
0 : more than half
1 : less than half
Receive FIFO half level status (Read only)
0 : less than half
1 : more than half
Transmit FIFO ready flag (Read only)
0 : Not ready (empty)
1 : Ready (not empty)
Receive FIFO ready flag (Read only)
0 : Not ready (full)
0b
0b
0b
0b
1 : Ready (not full)
15 : 8
7 : 0
R
R
Transmit FIFO data count (Read only)
Data count value : 0 ~ 16
Receive FIFO data count (Read only)
Data count value : 0 ~ 16
0h
0h
Left / Right channel index bit indicates the current LRCK state. The initially output state is always left by default
The Transmit / Receive FIFO half level status bit indicates the half level status of Tx / Rx FIFO. In transmit mode, a
value of ‘1’ represents the FIFO status below half level. In receive mode, a ‘1’ indicates the FIFO is above half level.
The Transmit / Receive FIFO ready flag bit indicates the ready status of each FIFO when I2S is enabled.
The Transmit / Receive FIFO data count bits indicate the level of each FIFO. This is a read-only register.
3.21.3.5 I2S Data Register (I2SDATA)
This is a data register for transmit / receive operation
Address: FFE0 9410h
Bit
R/W
Description
Default Value
31 : 0
R/W
I2S Data (Tx / Rx)
0h
171
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