EAGLE
PRELIMINARY
Ver 1.3
3.21.4 Example for Register Set
3.21.4.1 To Start I2S operation
1) Set the I2SPS register.
2) Set the Tx / Rx operation in I2SMOD register separately.
3) For transmit mode, fills the Tx FIFO with dummy values. For receive mode, make sure the Rx FIFO is empty.
4) Enable the Interrupt / Request bit in I2SCON register.
5) Enable I2S.
3.21.4.2 To End I2S operation
1) Disable Interrupt / Request bit in I2SCON.
2) Disable I2S. ( Disable I2S after confirming the FIFO Level bit in I2SSTAT register is ‘0’ to ensure that all data in
FIFO has been transmitted or received).
3) Clear I2SMOD register.
3.21.5 Audio Serial Interface Format
3.21.5.1 I2S-bus format
The I2S bus has four lines known as serial data input (I2S DIN), serial data output (I2S DOUT), left / right channel select
(LRCK) and serial bit clock (SCLK). the device which generates LRCK and SCLK shall acts as the master. Serial data is
transmitted in 2’s complement with MSB first. MSB is transmitted first because the transmitter and receiver may have
different word lengths. The transmitter does not have to know how many bits the receiver can handle, nor does the receiver
need to know how many bits are being transmitted. For data transmission, when the system word length is greater than the
transmitter word length, the word is truncated (least significant data bits are set to ‘0’). If the receiver gets more bits than its
word length, the bits after LSB are ignored. On the other hand, if the receiver gets fewer bits than its word length, the
missing bits are set to zero internally. This architecture ensures that the MSB has a fixed position while the position of the
LSB depends on the word length. The transmitter sends the MSB of the next word at the next immediate serial clock after
LRCK signal toggles. Serial data sent by the transmitter is synchronized with either the trailing (HIGH to LOW) or leading
(LOW to HIGH) edge of the clock signal. When data transmission is synchronized to the leading clock edge, receiver must
ensure that data is latched in on the leading edge of the serial clock signal. The LR channel select line indicates the channel
used for transmission.. LRCK may be changed on a trailing or leading edge of the serial clock, and it does not need to be
symmetrical.. In slave, LRCK signal is latched on the leading edge of the clock signal. Since LRCK line toggles one clock
period before the MSB is transmitted, this allows the slave transmitter to synchronous the timing of the serial data set-up for
transmission. Furthermore, this enables the receiver to store the previous received word to clear the input for next word.
3.21.5.2 MSB(Left)-justified format
The MSB (left)-justified bus format is the same as I2S bus format in terms of architecture. The only difference being that
the MSB-justified format knows when to expect for the MSB of the next word by referring to the LRCK signal.
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