欢迎访问ic37.com |
会员登录 免费注册
发布采购

PKM32AG-Q 参数 Datasheet PDF下载

PKM32AG-Q图片预览
型号: PKM32AG-Q
PDF下载: 下载PDF文件 查看货源
内容描述: EAGLE是一款多媒体处理器.EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。 [EAGLE是一款多媒体处理器。EAGLE集成了带有DSP特性的32位EISC CPU处理器、H.264解码器、JPEG解码器、2D图像引擎、声音混音器、具有OSD功能的CRT控制器、视频编码器、视频解码接口模块、USB主/从和通用I/O外设接口。]
分类和应用: 解码器编码器控制器
文件页数/大小: 235 页 / 4257 K
品牌: ETC [ ETC ]
 浏览型号PKM32AG-Q的Datasheet PDF文件第99页浏览型号PKM32AG-Q的Datasheet PDF文件第100页浏览型号PKM32AG-Q的Datasheet PDF文件第101页浏览型号PKM32AG-Q的Datasheet PDF文件第102页浏览型号PKM32AG-Q的Datasheet PDF文件第104页浏览型号PKM32AG-Q的Datasheet PDF文件第105页浏览型号PKM32AG-Q的Datasheet PDF文件第106页浏览型号PKM32AG-Q的Datasheet PDF文件第107页  
Ver 1.3  
PRELIMINARY  
EAGLE  
3.9.3.8 Bit-stream Buffer New Read Address Register (H264BRAW)  
During the operation of H.264 Decoder, this register provides user the capability to access new Bit-stream buffer region  
by configuring the new read address in the Bit-Stream Buffer new Read Address register  
Address: FFE0 1C1Ch  
Bit  
R/W  
Description  
Default Value  
31 : 0  
R/W  
Bit-stream Buffer new read address for modification  
0h  
By default, this register is set to the same value as H264BSA register.  
3.9.4 Decoded Image Related Registers  
3.9.4.1 Y0 Frame Buffer Start Address Register (H264Y0SA)  
This register configures the Y0 Frame Buffer region which contains decoded Images stored by the H.264 Decoder.  
Address: FFE0 1C20h  
Bit  
31 : 0  
R/W  
R/W  
Description  
Frame_Buffer_Y0 Start Address  
Default Value  
0h  
Decoder uses 3 Frame Buffers for Y(Luminance). Scaler reads the Start Address of Y Frame Buffer from Decoder  
during bank switching through Frame Sync signal synchronization.  
3.9.4.2 Y1 Frame Buffer Start Address Register (H264Y1SA)  
This register configures the Y1 Frame Buffer region which contains decoded Images stored by the H.264 Decoder.  
Address: FFE0 1C24h  
Bit  
31 : 0  
R/W  
R/W  
Description  
Frame_Buffer_Y1 Start Address  
Default Value  
0h  
3.9.4.3 Y2 Frame Buffer Start Address Register (H264Y2SA)  
This register configures the Y2 Frame Buffer region which contains decoded Images stored by the H.264 Decoder.  
Address: FFE0 1C28h  
Bit  
31 : 0  
R/W  
R/W  
Description  
Frame_Buffer_Y2 Start Address  
Default Value  
0h  
3.9.4.4 C0 Frame Buffer Start Address Register (H264C0SA)  
This register configures the C0 Frame Buffer region which contains decoded Images stored by the H.264 Decoder.  
Address: FFE0 1C2Ch  
Bit  
31 : 0  
R/W  
R/W  
Description  
Frame_Buffer_C0 Start Address  
Default Value  
0h  
Decoder uses 3 Frame Buffers for C(Chrominance). Scaler reads the Start Address of C Frame Buffer from Decoder  
during bank switching through Frame Sync signal synchronization.  
103  
CONFIDENTIAL  
Beijing Peak Microtech Co.Ltd.  
 复制成功!