EAGLE
PRELIMINARY
(and H/W Based Decoding for the rest)
Ver 1.3
Decoder mode register allows mode switching between fully hardware-based decoding mode and hardware-software
mixed decoding mode. The default value is set to fully hardware-based decoding mode.
3.9.3.3 Decoder Endian Register (H264ENDIAN)
This register programs the Decoder Endian format.
Address: FFE0 1C08h
Bit
31 : 1
0
R/W
R
R/W
Description
Default Value
Reserved
Decoder Endian
-
0b
0 : Decoder Big Endian
1 : Decoder Little Endian
The default setting of Decoder Endian bit is Big Endian. However, user may reconfigure the decoder endian to Little
Endian format.
3.9.3.4 Error Detection Register (H264ERRON)
This register supports the Error Detection capability of H.264 Decoder
Address: FFE0 1C0Ch
Bit
31 : 1
0
R/W
R
R/W
Description
Default Value
Reserved
Error Detection
-
1b
0 : Disable Error Detection Operation
1 : Enable Error Detection Operation (default)
Error Detection register enables error detection operation during the data bit-stream decoding process. If an error is
detected, the decoding process and error detection operation shall resume after the next slice Start Code is found.
3.9.3.5 Bit-stream Buffer Start Address Register (H264BSA)
This register programs the Start Address of the bit-stream buffer
Address: FFE0 1C10h
Bit
R/W
Description
Default Value
31 : 0
R/W
Bit-stream buffer start address
0h
The Bit-stream Buffer Start Address register is used together with the Bit-stream Buffer End Address register to
allocate external memory space (area) for data bit-stream buffering purposes.
3.9.3.6 Bit-stream Buffer End Address Register (H264BEA)
This register programs the End Address of Bit-stream buffer
Address: FFE0 1C14h
Bit
R/W
Description
Default Value
31 : 0
R/W
Bit-stream buffer end address
0h
3.9.3.7 Bit-stream Buffer Read Address Register (H264BRA)
This register shows the current read address of bit-stream buffer.
Address: FFE0 1C18h
Bit
R/W
Description
Default Value
31 : 0
R
Bit-stream Buffer read address by decoder
0h
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ETC [ ETC ]
