EAGLE
PRELIMINARY
Ver 1.3
3.8 Graphic Controller
3.8.1 Packet Write Pointer Register (GRAPWP)
Address : FFE0 1800h
Bit
R/W
Description
Default Value
31 : 11
10 : 0
R
R/W
Reserved
Command packet Write pointer
-
000h
(When the Engine becomes inactive, it is reset to ‘0’)
3.8.2
Packet Read Pointer Register (GRAPRP)
Address : FFE0 1804h
Bit
31 : 11
10 : 0
R/W
R
R/W
Description
Default Value
Reserved
-
Command packet Read pointer ( Half Word Access Only )
1. This value is increased after reading current command packet. When
the engine becomes inactive, this bit is reset to ‘0’.
000h
2. This value is set when the engine is in inactive state.
3.8.3 Rendering Control Register (GRARCON)
Address : FFE0 1808h
Bit
31 : 14
13 : 12
R/W
R
R/W
Description
Default Value
Reserved
-
Write FIFO Memory Request Level
00 : ¼ Full
01 : ½ Full
1x : ¾ Full
Reserved
01b
-
11 : 9
8
R
R/W
EndRender Write FIFO Flush Enable
0: Disable EndRender Flush Operation.
1: Enable EndRender Flush Operation.
Note) Pixel FIFO Flush operation is always executed before the Flip
Command is allowed to proceed. In such case, this bit need not be set
0b
during the execution of Buffer Switching operation using Flip Command.
However if this bit is set, Pixel FIFO Flush shall be executed whenever
the packet terminates.
Dithering mode
7 : 6
R/W
00 : Disable.
01 : 2X2 dithering
00b
1X : 4X4 dithering
5
4
R
R/W
Reserved
-
Rendering Buffer Select
0 : Render to Back buffer ( Double Buffer mode )
1 : Render to Front buffer ( Single Buffer mode )
Reserved
Rendering Engine Enable
0 : Disable
0b
3 : 1
0
R
R/W
-
0b
1 : Enable
* For Control register bit[4] ( Rendering Buffer Select ) : Refer to CSC Image Capturer Control register bit[0]
Beijing Peak Microtech Co.Ltd.
CONFIDENTIAL
98
ETC [ ETC ]
