ADM7008
Register Description
Interface
Bit #
Name Description
Type Default
0: Not capable of auto negotiation
TP : This bit is set to 1 all the time,
indicating that PHY841F is capable of
auto negotiation.
FX : This bit is set to 0 all the time,
indicating that PHY841F is not capable
of auto negotiation in Fiber Mode.
2
LINK
RO,
LL
0h Updated By Per
port Link
Link Status
1: Link is up
Monitor
0: Link is down
This bit reflects the current state of the
link -test-fail state machine. Loss of a
valid link causes a 0 latched into this bit.
It remains 0 until this register is read by
the serial management interface.
Whenever Linkup, this bit should be read
twice to get link up status
1
0
JAB
RO,
LH
0h Updated by Per
port Jabber
Jabber Detect
1: Jabber condition detected
0: Jabber condition not detected
Detector
EXTREG
RO
1h
Extended Capability
1: Extended register set
0: No extended register set
This bit defaults to 1, indicating that the
PHY841F implements extended registers.
4.3.3 PHY Identifier Register (Register 2h)
Bit #
Name
Description
Type Default
Interface
15:0
PHY- IEEE Address
ID[15:0]
RO 002E Rg2_PHY_ID
Input
4.3.4 PHY Identifier Register (Register 3h)
Bit #
Name
Description
Type Default
Interface
15:10
PHY- IEEE Address/Model No./Rev. No.
ID[15:0]
RO CC10 RG3_PHY_ID
Input
9:4 MODEL[5: ADMTEK PHY Revision ID.
0]
RO CC10 RG3_MODEL_I
D Input
3:0
REV- ADMTEK PHY Revision ID.
ID[3:0]
RO 4 h0 Rev_id input
ADMtek Inc.
4-8
ETC [ ETC ]
