ADM7008
Register Description
Interface
Bit #
Name Description
Type Default
disabled (bit12 = 0). The specific PHY
(10Base-T or 100Base-X) used for this
operation is determined by bits 12 and
13.
13 SPEED_LS
R/W
1h When Auto
Negotiation is
enable, this pin
has no effect.
Speed Selection LSB
B
0.60.13
0 0
0 1
1 0
1 1
10 Mbps
100 Mbps
1000 Mbps
Reserved
Link speed is selected by this bit or by
auto negotiation if bit 12 of this register
is set (in which case, the value of this bit
is ignored).
12
11
ANEN
PDN
R/W
R/W
1h This bit ANDed
with
Auto Negotiation Enable
1: Enable auto negotiation process
0: Disable Auto negotiation process
This bit determines whether the link
speed should set up by the auto
negotiation process or not. It is set at
power up or reset if the PI_RECANEN
pin detects a logic 1 input level in
Twisted-Pair Mode.
PI_RECANEN
pin determines
auto negotiation
capability of
PHY841F.
0h 1.Only Access
through
Power Down Enable
1: Power Down
MDC/MDIO
0: Normal Operation
Ored result with PI_PWRDN pin.
Setting this bit high or asserting the
PI_PWRDN puts the PHY841F into
power down mode. During the power
down mode, TXP/TXN and all LED
outputs are tri-stated and the MII/RMII
interfaces are isolated.
10
ISO
R/W
0h 1.Only Access
through
Isolate PHY841F from Network
1: Isolate PHY from MII/RMII
MDC/MDIO
2.Used to reset
corresponding
port.
0: Normal Operation
Setting this control bit isolates the part
from the RMII/MII, with the exception of
the serial management interface. When
this bit is asserted, the PHY841F does not
respond to TXD, TXEN and TXER
inputs, and it presents a high impedence
on its TXC, RXC, CRSDV, RXER,
RXD, COL and CRS outputs.
ADMtek Inc.
4-5
ETC [ ETC ]
