ADM7008
Register Description
Interface
Bit #
Name Description
Type Default
9
ANEN_RS
T
R/W
SC
0h
Restart Auto Negotiation
1: Restart Auto Negotiation Process
0: Normal Operation
Setting this bit while auto negotiation is
enabled forces a new auto negotiation
process to start. This bit is self-clearing
and returns to 0 after the auto negotiation
process has commenced.
8
DPLX
R/W
R/W
0h This bit Ored
with RECFUL
pin determines
the duplex
Duplex Mode
1: Full Duplex mode
0: Half Duplex mode
If auto negotiation is disabled, this bit
determines the duplex mode for the link.
capability of
PHY841F when
ANEN disabled.
0h
7
6
COLTST
Collision Test
1: Enable COL signal test
0: Disable COL signal test
When set, this bit will cause the COL
signal of MII interface to be asserted in
response to the assertion of TXEN.
SPEED_M
SB
RO
RO
0h Always 0.
00h Always 0.
Speed Selection MSB
Set to 0 all the time indicate that the
PHY841F does not support 1000 Mbps
function.
5:0 Reserved
4.3.2 Status (Register 1h)
Bit #
Name Description
Type Default
Interface
15
CAP_T4
RO
0h
100Base-T4 Capable
Set to 0 all the time to indicate that the
PHY841F does not support 100Base-T4
14 CAP_TXF 100Base-X Full Duplex Capable
Set to 1 all the time to indicate that the
PHY841F does support Full Duplex
mode
RO
1h
13 CAP_TXH 100Base-X Half Duplex Capable
Set to 1 all the time to indicate that the
PHY841F does support Half Duplex
mode
RO
RO
1h
1h
12
CAP_TF
10M Full Duplex Capable
TP : Set to 1 all the time to indicate that
the PHY841F does support 10M Full
ADMtek Inc.
4-6
ETC [ ETC ]
