ADM7008
Register Description
4.2.18 Register #1dh – Receive Error Counter
15
ERB15 ERB14 ERB13 ERB12 ERB11 ERB10 ERB9
RO RO RO RO RO RO RO
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ERB8
RO
ERB7
RO
ERB6
RO
ERB5
RO
ERB4
RO
ERB3
RO
ERB2
RO
ERB1
RO
ERB0
RO
4.2.19 Register #1eh – Chip ID (8888)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CID33 CID32 CID31 CID30 CID23 CID22 CID21 CID20 CID13 CID12 CID11 CID10 CID03 CID02 CID01 CID00
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
4.2.20 Register #1fh –Total Interrupt Status (only For Port 0)
15
INT7
RO
14
INT6
RO
13
INT5
RO
12
INT4
RO
11
INT3
RO
10
INT2
RO
9
8
7
6
5
4
0
3
0
2
0
1
0
0
0
INT1
RO
INT0
RO
0
0
0
RO
RO
RO
RO
RO
RO
RO
RO
4.3 Register Description
4.3.1 Control (Register 0h)
Bit #
Name Description
Type Default
Interface
15
RST
R/W
SC
0h 1.Updated by
MDC/MDIO.
2.Connect to
Central
RESET
1: PHY Reset
0: Normal operation
Setting this bit initiates the software reset
function that resets the selected port,
except for the phase-locked loop circuit.
It will re-latch in all hardware
Control Block
to Generate
Reset Signal.
configuration pin values. The software
reset process takes 25us to complete.
This bit, which is self-clearing, returns a
value of 1 until the reset process is
complete.
14
LPBK
R/W
0h 1.Updated by
MDC/MDIO
Only.
Back Enable
1:Enable loop back mode
0: Disable Loop back mode
Control the Wire
connection in
Driver
This bit controls the PHY loop back
operation that isolates the network
transmitter outputs (TXP and TXN) and
routes the MII transmit data to the MII
receive data path. This function should
only be used when auto negotiation is
ADMtek Inc.
4-4
ETC [ ETC ]
