ADM7008
Function Description
timing diagram for 10M Transmission.
REFCLK
TXEN_P
00
00
01
Data
Data
TXD_P
Preamble/SFD Transition once every 10 cycles
Data Transition once every 10 cycles
Figure 3-10 10M RMII Transmit Diagram
Recommend Value
Auto Negotiation
Enable Disable 100 Full 100 Half 10 Full 10 Half
Capability
REC_10M
ANENDIS
TP_FULLDUPLEX
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
Table 3-2 Channel Configuration
3.2.6 Serial and Source Synchronous Media Independent Interface
The Synchronous Media Independent Interface (SMII) conforms to the SMII
specification Rev. 2.1. The REFCLK pin that supplies the 125MHz reference clock to the
ADM7008 is used as the SMII/Serial and Source Synchronous Media Independent
Interface (SS_SMII) reference clock.
All SMII/SS_SMII signals are synchronous to REFCLK. The differences between SMII
and SS_SMII are
1.SMII shares the same SYNC signal from MAC yet SS_SMII take TX_SYNC signal as
synchronization input for transmission and output RX_SYNC to MAC for reception
synchronization usage.
2.SMII use REFCLK (125MHz) for both receive and transmit blocks. SS_SMII takes
TXCLK as transmit block reference clock and output an 125MHz RXCLK to MAC for
receive usage. All signals output from ADM7008 are synchronous to RXCLK.
In this mode, REFCLK will be divided by 5 to generate 25M clock before it is fed into
ADM7008 internal PLL block. SS_SMII mode is enabled by setting RSMODE1 (pin 43)
ADMtek Inc.
3-17
ETC [ ETC ]
