ADM7008
Function Description
In SMII mode, when RXDV bit is high, RXD[7:0] are used to convey packet data; when
RXDV bit is low, RXD[7:0] are carrying PHY status. See Table 3-3 for more detail.
CRS
X
RXDV
RXD0
RXER From
Previous
Frame
RXD1
Speed
RXD2
Duplex
RXD3
Link
RXD4
Jabber
RXD5
Upper
Nibble
RXD6
False
Carrier
RXD7
0
1
0 = 10Mb/s 0 = Half
1 =
100Mb/s
0 = Down
1 = Up
0 = O.K. 0 = Invalid
1 = Error 1 = Valid
1 = Full
0 = NO
1 =
Detected
X
1
One Data Byte (Two MII Data Nibble)
Table 3-3 Receive Data Encoding for SMII/SS_SMII mode
3.2.8 10M Receive Path
Similar to 100M Receive path except that each segment is repeated 10 times. The MAC
can sample any one of every 10 segments in 10BASE-T mode. The MAC also has to
generate a SYNC pulse once every 10 clock cycles.
REFCLK
SYNC
CRS_
1
CRS_
1
CRS_
2
RXD7_
0
RXDV_ RXD0_ RXD1_ RXD2_ RXD3_ RXD4_ RXD5_ RXD6_ RXD7_
RXDV_ RXD0_ RXD1_ RXD2_ RXD3_ RXD4_ RXD5_ RXD6_ RXD7_
RXDV_ RXD0_
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
RXD_P
Data Repeated 10 Times (Use 10 SYNC for 1 Byte Data)
Figure 3-15 10M SMII Receive Timing Diagram
RXCLK_SSMII
SYNC_RX
RXD_P
CRS_
1
CRS_
1
CRS_
2
RXD7_
0
RXDV_ RXD0_ RXD1_ RXD2_ RXD3_ RXD4_ RXD5_ RXD6_ RXD7_
RXDV_ RXD0_ RXD1_ RXD2_ RXD3_ RXD4_ RXD5_ RXD6_ RXD7_
RXDV_ RXD0_
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
Data Repeated 10 Times (Use 10 SYNC_RX for 1 Byte Data)
Figure 3-16 10M SS_SMII Receive Timing Diagram
ADMtek Inc.
3-19
ETC [ ETC ]
