ADM7008
Function Description
3.2.9 100M Transmit Path
Similar to 100M Receive path, transmit data is grouped in 10-bit segments that are
delimited by the SYNC signal (or TX_SYNC in SS_SMII mode), each segment
represents a new byte of data. See Figure 3-17 for 100M SMII transmit timing diagram
and Figure 3-18 for SS_SMII timing diagram.
In SS_SMII mode, REFCLK and SYNC are no longer commonly used for both transmit
and receive blocks. They are renamed to TXCLK and TX_SYNC. When TXEN bit is
low, data on TXD[7:0] will be ignored by ADM7008. See Table 3-4 transmit data
encoding for more detail.
REFCLK
SYNC
TXD7 TXER TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXER TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXER TXEN TXD0 TXD1 TXD2
TXD_P
Figure 3-17 100M SMII Transmit Timing Diagram
TXCLK_SSMII
SYNC_TX
TXD_P
TXD7 TXER TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXER TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXER TXEN TXD0 TXD1 TXD2
Figure 3-18 100M SS_SMII Transmit Timing Diagram
3.2.10 10M Transmit Path
In 10BASE-T mode, each segment must be repeated 10 times by the MAC. In this mode,
the MAC must generate the same data in each of the 10 segments. ADM7008 will
sample the incoming data at the 5th SYNC (or SYNC_TX) location.
REFCLK
SYNC
TXD7_ TXER_ TXEN_ TXD0_ TXD1_ TXD2_ TXD3_ TXD4_ TXD5_ TXD6_ TXD7_
TXER_ TXEN_ TXD0_ TXD1_ TXD2_ TXD3_ TXD4_ TXD5_ TXD6_ TXD7_ TXER_ TXEN_ TXD0_
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
TXD_P
Data Repeated 10 Times (Use 10 SYNC for 1 Byte Data)
Figure 3-19 10M SMII Transmit Timing Diagram
ADMtek Inc.
3-20
ETC [ ETC ]
