ADM7008
Function Description
3.2.1 Reduced Media Independent Interface (RMII)
The reduced media Independent interface (RMII) is compliant to the RMII consortium’s
RMII Rev. 1.2 specification. The REFCLK pin that supplies the 50 MHz reference clock
to the AD2106 is used as the RMII REFCLK signal. All RMII signals with the exception
of the assertion of CRSDV_P are synchronous to REFCLK.
TXEN
TXD0
TXD1
CRSDV
MAC
PHY
RXD0
RXD1
RXER
REFCLK
Figure 3-4 RMII Signal Diagram
3.2.2 Receive Path for 100M
Figure 3-5 shows the relationship among REFCLK, CRSDV_P, RXD0_P, RXD1_P and
RXER_P while receiving a valid packet. Carrier sense is detected, which causes
CRSDV_P to assert asynchronously to REFCLK. The received data is then placed into
the FIFO for resynchronization. After a minimum of 12 bits are placed into the FIFO, the
received data is presented onto RXD[1:0]_P synchronously to REFCLK. Note that while
the FIFO is filling up RXD[1:0]_P is set to 00 until the first received di-bit of preamble
(01) is presented onto RXD[1:0]_P. When carrier sense is de-asserted at the end of a
packet, CRSDV_P is de-asserted when the first di-bit of a nibble is presented onto
RXD[1:0]_P synchronously to REFCLK. If there is still data in the FIFO that has not yet
been presented onto RXD[1:0]_P, then on the second di-bit of a nibble, CRSDV_P
reasserts. This pattern of assertion and de-assertion continues until all received data in
the FIFO has been presented onto RXD[1:0]_P. RXER_P is inactive for the duration of
the received valid packet.
Figure 3-6 shows the relationship among REFCLK, CRSDV_P and RXD[1:0]_P during a
received false carrier event. CRSDV_P is asserted asynchronously to REFCLK as in the
valid receive case shown in Figure 3-5. However, once false carrier is detected,
RXD[1:0]_P is changed to (10) (11) (Value 1110 in MII) and RXER_P is asserted. Both
RXD[1:0]_P and RXER_P transition synchronously to REFCLK. After carrier sense is
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