ADM7008
Function Description
to low and placing a pull up resistor on CRSDV_P6. In this mode, CRSDV_P[3]
becomes RX_SYNC, CRSDV_P4 becomes RXCLK and TXEN_P4 acts as TX_SYNC.
TXCLK_SSMII
SYNC_TX
SYNC
TXD0_P[7:0]
TXD0_P[7:0]
MAC
PHY
MAC
PHY
RXD0_P[7:0]
REFCLK
RXCLK_SSMII
SYNC_RX
RXD0_P[7:0]
Figure 3-12 SS_SMII Signal Diagram
Figure 3-11 SMII Signal Diagram
3.2.7 100M Receive Path
Received data and control information is grouped in 10-bit segments that are delimited by
the SYNC signal in SMII mode (or SYNC_RX in SS_SMII mode) as shown in figure 15.
Each segment represents a new byte of data.
REFCLK
SYNC
RXD7 CRS RXDV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 CRS RXDV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 CRS RXDV RXD0 RXD1 RXD2
RXD_P
Figure 3-13 100M SMII Receive Timing Diagram
In SS_SMII mode, REFCLK and SYNC are no longer common for both transmit and
receive blocks. They are renamed to RXCLK and RX_SYNC.
RXCLK_SSMII
SYNC_RX
RXD_P
RXD
V
RXD
V
RXD
V
RXD7 CRS
RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 CRS
RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 CRS
RXD0 RXD1 RXD2
Figure 3-14 100M SS_SMII Receive Timing Diagram
ADMtek Inc.
3-18
ETC [ ETC ]
