ADM7008
Function Description
3.2.3 Receive Path for 10M
REFCLK
CRSDV
RXD
00
00
01
Data
Data
Preamble/SFDTransitiononceevery10cycles
DataTransitiononceevery10cycles
Figure 3-8 10M RMII Receive Diagram
In 10M Mode, RXER_P will maintain low all the time due to False Carrier and symbol
error is not supported by 10M Mode. Different from 100M mode, RXD_P and
CRSDV_P can transition once per 10 REFCLK cycles. After carrier sense is de-asserted
yet the FIFO data is not fully presented onto RXD_P, the CRSDV_P de-assertion and re-
assertion also follows this rule.
3.2.4 Transmit Path for 100M
Figure 3-9 shows the relationship among REFCLK, TXEN_P and TXD[1:0]_P during a
transmit event. TXEN_P and TXD[1:0]_P are synchronous to REFCLK. When TXEN_P
is asserted, it indicates that TXD[1:0]_P contains valid data to be transmitted. When
TXEN_P is de-asserted, value on TXD[1:0]_P should be ignored. If an odd number of
di-bits are presented onto TXD[1:0]_P and TXEN_P, the final di-bit will be discarded by
AD2106.
REFCLK
TXEN
00
00
01
01
01
01
01
01
01
01
01
11 Data Data
Data Data Data Data Data Data Data 00
Data
00
00
TXD[1:0]
Preamble
SFD
Figure 3-9 100M RMII Transmit Diagram
3.2.5 Transmit Path for 10M
In 10MBSE-T mode, each di-bit must be repeated 10 times by the MAC, TXEN_P and
TXD[1:0]_P should be synchronous to REFCLK. When TXEN_P is asserted, it indicates
that data on TXD[1:0]_P is valid for transmission.
In 10BASE-T mode, it is possible that the number of preamble bits and the number of
frame bits received are not integer nibbles. The preamble is always padded up such that
the SFD appears on the RMII aligned to the nibble boundary. Extra bits at the end of the
frame that do not complete a nibble are truncated by AD2106. Figure 12 shows the
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3-16
ETC [ ETC ]
