ST6200C/ST6201C/ST6203C
RESET (Cont’d)
5.3.4 Watchdog Reset
Figure 16. Reset Processing
The MCU provides a Watchdog timer function in
order to be able to recover from software hang-
ups. If the Watchdog register is not refreshed be-
fore an end-of-count condition is reached, a
Watchdog reset is generated.
RESET
2048
CLOCK CYCLE
DELAY
After a Watchdog reset, the MCU restarts in the
same way as if a Reset was generated by the RE-
SET pin.
INTERNAL
RESET
Note: When a watchdog reset occurs, the RESET
pin is tied low for very short time period, to flag the
reset phase. This time is not long enough to reset
external circuits.
NMI MASK SET
INT LATCH CLEARED
(IF PRESENT)
For more details refer to the Watchdog Timer
chapter.
SELECT
NMI MODE FLAGS
5.3.5 LVD Reset
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■ Power-On RESET
PUT FFEh
■ Voltage Drop RESET
ON ADDRESS BUS
During an LVD reset, the RESET pin is pulled low
when V <VIT+ (rising edge) or V <VIT- (falling
DD
DD
edge).
YES
For more details, refer to the LVD chapter.
IS RESET STILL
PRESENT?
Caution: Do not externally connect directly the
RESET pin to VDD, this may cause damage to the
component in case of internal RESET (Watchdog
or LVD).
NO
LOAD PC
FROM RESET LOCATIONS
Figure 15. Simple external Reset Circuitry
FFEh/FFFh
V
V
DD
DD
FETCH INSTRUCTION
R
C
RESET
ST62xx
R > 4.7 K
Typical: R = 10K
C = 10nF
25/104
1
ETC [ ETC ]
