PIC16F87X
9.2.3
SLEEP OPERATION
9.2.4
EFFECTS OF A RESET
2
While in sleep mode, the I C module can receive
addresses or data. When an address match or com-
plete byte transfer occurs, wake the processor from
sleep (if the SSP interrupt is enabled).
A reset disables the SSP module and terminates the
current transfer.
2
TABLE 9-3
Address
REGISTERS ASSOCIATED WITH I C OPERATION
POR,
BOR
MCLR,
WDT
Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
0Dh
8Dh
13h
14h
91h
94h
PIR1
PSPIF(1)
PSPIE(1)
—
ADIF
ADIE
(2)
RCIF
RCIE
—
TXIF
TXIE
EEIF
EEIE
SSPIF
SSPIE
BCLIF
BCLIE
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE1
PIR2
—
—
—
—
CCP2IF -r-0 0--0 -r-0 0--0
CCP2IE -r-0 0--0 -r-0 0--0
xxxx xxxx uuuu uuuu
PIE2
—
(2)
—
SSPBUF
SSPCON
SSPCON2
SSPSTAT
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
GCEN
SMP
SSPOV
ACKSTAT
CKE
SSPEN
ACKDT
D/A
CKP
ACKEN
P
SSPM3 SSPM2
SSPM1
RSEN
UA
SSPM0 0000 0000 0000 0000
RCEN
S
PEN
R/W
SEN
0000 0000 0000 0000
0000 0000 0000 0000
BF
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in I2C mode.
Note 1: These bits are reserved on the 28-pin devices; always maintain these bits clear.
2: These bits are reserved on these devices; always maintain these bits clear.
1999 Microchip Technology Inc.
DS30292B-page 75
ETC [ ETC ]
