PIC16F87X
2
9.2.9
I C MASTER MODE START CONDITION
TIMING
Note: If at the beginning of START condition the
SDA and SCL pins are already sampled
low, or if during the START condition the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs, the
Bus Collision Interrupt Flag (BCLIF) is set,
the START condition is aborted, and the
To initiate a START condition, the user sets the start
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is re-loaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (TBRG), the
SDA pin is driven low. The action of the SDA being
driven low while SCL is high is the START condition,
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (TBRG), the
SEN bit (SSPCON2<0>) will be automatically cleared
by hardware. The baud rate generator is suspended
leaving the SDA line held low, and the START condition
is complete.
2
I C module is reset into its IDLE state.
9.2.9.1
WCOL STATUS FLAG
If the user writes the SSPBUF when an START
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
Note: Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.
FIGURE 9-12: FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here.
SDA = 1,
At completion of start bit,
Hardware clears SEN bit
and sets SSPIF bit
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
1st Bit 2nd Bit
SDA
TBRG
SCL
TBRG
S
1999 Microchip Technology Inc.
DS30292B-page 79
ETC [ ETC ]
