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PIC16F877T-20PQ 参数 Datasheet PDF下载

PIC16F877T-20PQ图片预览
型号: PIC16F877T-20PQ
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器\n [8-Bit Microcontroller ]
分类和应用: 微控制器
文件页数/大小: 200 页 / 3338 K
品牌: ETC [ ETC ]
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PIC16F87X  
i) The MSSP module shifts in the ACK bit from the  
slave device, and writes its value into the  
SSPCON2 register ( SSPCON2<6>).  
In I2C master mode, the BRG is reloaded automatically.  
If Clock Arbitration is taking place for instance, the BRG  
will be reloaded when the SCL pin is sampled high  
(Figure 9-11).  
j) The MSSP module generates an interrupt at the  
end of the ninth clock cycle by setting the SSPIF  
bit.  
FIGURE 9-10: BAUD RATE GENERATOR  
BLOCK DIAGRAM  
k) The user generates a STOP condition by setting  
the STOP enable bit PEN in SSPCON2.  
SSPM3:SSPM0  
SSPADD<6:0>  
l) Interrupt is generated once the STOP condition  
is complete.  
9.2.8  
BAUD RATE GENERATOR  
SSPM3:SSPM0  
SCL  
Reload  
Control  
Reload  
2
In I C master mode, the reload value for the BRG is  
located in the lower 7 bits of the SSPADD register  
(Figure 9-10). When the BRG is loaded with this value,  
the BRG counts down to 0 and stops until another  
reload has taken place. The BRG count is decremented  
twice per instruction cycle (TCY), on the Q2 and Q4  
clock.  
FOSC/4  
BRG Down Counter  
CLKOUT  
FIGURE 9-11: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION  
SDA  
DX  
DX-1  
SCL allowed to transition high  
SCL deasserted but slave holds  
SCL low (clock arbitration)  
SCL  
BRG decrements  
(on Q2 and Q4 cycles)  
BRG  
value  
03h  
02h  
01h  
00h (hold off)  
03h  
02h  
SCL is sampled high, reload takes  
place, and BRG starts its count.  
BRG  
reload  
DS30292B-page 78  
1999 Microchip Technology Inc.  
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