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PIC16F877T-20PQ 参数 Datasheet PDF下载

PIC16F877T-20PQ图片预览
型号: PIC16F877T-20PQ
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器\n [8-Bit Microcontroller ]
分类和应用: 微控制器
文件页数/大小: 200 页 / 3338 K
品牌: ETC [ ETC ]
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PIC16F87X  
2
Two pins are used for data transfer. These are the SCL  
pin, which is the clock, and the SDA pin, which is the  
data. The SDA and SCL pins are automatically config-  
ured when the I C mode is enabled. The SSP module  
functions are enabled by setting SSP Enable bit  
SSPEN (SSPCON<5>).  
9.2  
MSSP I C Operation  
2
The MSSP module in I C mode fully implements all  
master and slave functions (including general call sup-  
port) and provides interrupts-on-start and stop bits in  
hardware to determine a free bus (multi-master func-  
tion). The MSSP module implements the standard  
mode specifications, as well as 7-bit and 10-bit  
addressing.  
2
2
The MSSP module has six registers for I C operation.  
They are the:  
• SSP Control Register (SSPCON)  
• SSP Control Register2 (SSPCON2)  
• SSP Status Register (SSPSTAT)  
• Serial Receive/Transmit Buffer (SSPBUF)  
• SSP Shift Register (SSPSR) - Not directly acces-  
sible  
Refer to Application Note AN578, "Use of the SSP  
Module in the I C Multi-Master Environment."  
2
A "glitch" filter is on the SCL and SDA pins when the pin  
is an input. This filter operates in both the 100 kHz and  
400 kHz modes. In the 100 kHz mode, when these pins  
are an output, there is a slew rate control of the pin that  
is independant of device frequency.  
• SSP Address Register (SSPADD)  
2
The SSPCON register allows control of the I C opera-  
tion. Four mode selection bits (SSPCON<3:0>) allow  
one of the following I C modes to be selected:  
2
FIGURE 9-5: I C SLAVE MODE BLOCK  
2
DIAGRAM  
2
• I C Slave mode (7-bit address)  
Internal  
Data Bus  
2
• I C Slave mode (10-bit address)  
2
• I C Master mode, clock = OSC/4 (SSPADD +1)  
Read  
Write  
2
Before selecting any I C mode, the SCL and SDA pins  
must be programmed to inputs by setting the appropri-  
ate TRIS bits. Selecting an I C mode, by setting the  
SSPBUF reg  
SSPSR reg  
2
SCL  
SDA  
SSPEN bit, enables the SCL and SDA pins to be used  
Shift  
Clock  
2
as the clock and data lines in I C mode.  
The CKE bit (SSPSTAT<6:7>) sets the levels of the  
SDA and SCL pins in either master or slave mode.  
When CKE = 1, the levels will conform to the SMBUS  
specification. When CKE = 0, the levels will conform to  
MSb  
LSb  
Addr Match  
Match detect  
SSPADD reg  
2
the I C specification.  
Set, Reset  
S, P bits  
(SSPSTAT reg)  
Start and  
Stop bit detect  
1999 Microchip Technology Inc.  
DS30292B-page 71  
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