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PIC16F877T-20PQ 参数 Datasheet PDF下载

PIC16F877T-20PQ图片预览
型号: PIC16F877T-20PQ
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器\n [8-Bit Microcontroller ]
分类和应用: 微控制器
文件页数/大小: 200 页 / 3338 K
品牌: ETC [ ETC ]
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PIC16F87X  
The SSPSTAT register gives the status of the data  
transfer. This information includes detection of a  
START (S) or STOP (P) bit, specifies if the received  
byte was data or address, if the next byte is the comple-  
tion of 10-bit address, and if this will be a read or write  
data transfer.  
9.2.1.1  
ADDRESSING  
Once the MSSP module has been enabled, it waits for  
a START condition to occur. Following the START con-  
dition, the 8-bits are shifted into the SSPSR register. All  
incoming bits are sampled with the rising edge of the  
clock (SCL) line. The value of register SSPSR<7:1> is  
compared to the value of the SSPADD register. The  
address is compared on the falling edge of the eighth  
clock (SCL) pulse. If the addresses match, and the BF  
and SSPOV bits are clear, the following events occur:  
SSPBUF is the register to which the transfer data is  
written to or read from. The SSPSR register shifts the  
data in or out of the device. In receive operations, the  
SSPBUF and SSPSR create a doubled buffered  
receiver. This allows reception of the next byte to begin  
before reading the last byte of received data. When the  
complete byte is received, it is transferred to the  
SSPBUF register and flag bit SSPIF is set. If another  
complete byte is received before the SSPBUF register  
is read, a receiver overflow has occurred and bit  
SSPOV (SSPCON<6>) is set and the byte in the  
SSPSR is lost.  
a) The SSPSR register value is loaded into the  
SSPBUF register on the falling edge of the 8th  
SCL pulse.  
b) The buffer full bit, BF, is set on the falling edge of  
the 8th SCL pulse.  
c) An ACK pulse is generated.  
d) SSP interrupt flag bit, SSPIF (PIR1<3>), is set  
(interrupt is generated if enabled) on the falling  
edge of the 9th SCL pulse.  
The SSPADD register holds the slave address. In 10-bit  
mode, the user needs to write the high byte of the  
address (1111 0 A9 A8 0). Following the high byte  
address match, the low byte of the address needs to be  
loaded (A7:A0).  
In 10-bit address mode, two address bytes need to be  
received by the slave. The five Most Significant bits  
(MSbs) of the first address byte specify if this is a 10-bit  
address. Bit R/W (SSPSTAT<2>) must specify a write  
so the slave device will receive the second address  
byte. For a 10-bit address the first byte would equal  
1111 0 A9 A8 0’, where A9 and A8 are the two MSbs  
of the address. The sequence of events for a 10-bit  
address is as follows, with steps 7- 9 for slave-transmit-  
ter:  
9.2.1  
SLAVE MODE  
In slave mode, the SCL and SDA pins must be config-  
ured as inputs. The MSSP module will override the  
input state with the output data when required (slave-  
transmitter).  
When an address is matched or the data transfer after  
an address match is received, the hardware automati-  
cally will generate the acknowledge (ACK) pulse, and  
then load the SSPBUF register with the received value  
currently in the SSPSR register.  
1. Receive first (high) byte of Address (bits SSPIF,  
BF and UA (SSPSTAT<1>) are set).  
2. Update the SSPADD register with the second  
(low) byte of Address (clears bit UA and  
releases the SCL line).  
There are certain conditions that will cause the MSSP  
module not to give this ACK pulse. These are if either  
(or both):  
3. Read the SSPBUF register (clears bit BF) and  
clear flag bit SSPIF.  
4. Receive second (low) byte of Address (bits  
SSPIF, BF and UA are set).  
a) The buffer full bit BF (SSPSTAT<0>) was set  
before the transfer was received.  
5. Update the SSPADD register with the first (high)  
byte of Address. This will clear bit UA and  
release the SCL line.  
b) The overflow bit SSPOV (SSPCON<6>) was set  
before the transfer was received.  
If the BF bit is set, the SSPSR register value is not  
loaded into the SSPBUF, but bit SSPIF and SSPOV are  
set. Table 9-2 shows what happens when a data trans-  
fer byte is received, given the status of bits BF and  
SSPOV. The shaded cells show the condition where  
user software did not properly clear the overflow condi-  
tion. Flag bit BF is cleared by reading the SSPBUF reg-  
ister, while bit SSPOV is cleared through software.  
6. Read the SSPBUF register (clears bit BF) and  
clear flag bit SSPIF.  
7. Receive Repeated Start condition.  
8. Receive first (high) byte of Address (bits SSPIF  
and BF are set).  
9. Read the SSPBUF register (clears bit BF) and  
clear flag bit SSPIF.  
The SCL clock input must have a minimum high and  
low time for proper operation. The high and low times  
of the I C specification, as well as the requirement of  
the MSSP module, is shown in timing parameter #100  
and parameter #101 of the electrical specifications.  
Note: Following the Repeated Start condition  
(step 7) in 10-bit mode, the user only  
needs to match the first 7-bit address. The  
user does not update the SSPADD for the  
second half of the address.  
2
DS30292B-page 72  
1999 Microchip Technology Inc.  
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