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PIC16F877T-20PQ 参数 Datasheet PDF下载

PIC16F877T-20PQ图片预览
型号: PIC16F877T-20PQ
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器\n [8-Bit Microcontroller ]
分类和应用: 微控制器
文件页数/大小: 200 页 / 3338 K
品牌: ETC [ ETC ]
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PIC16F87X  
9.2.1.2  
SLAVE RECEPTION  
An SSP interrupt is generated for each data transfer  
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-  
ware. The SSPSTAT register is used to determine the  
status of the received byte.  
When the R/W bit of the address byte is clear and an  
address match occurs, the R/W bit of the SSPSTAT  
register is cleared. The received address is loaded into  
the SSPBUF register.  
Note: The SSPBUF will be loaded if the SSPOV  
bit is set and the BF flag is cleared. If a  
read of the SSPBUF was performed, but  
the user did not clear the state of the  
SSPOV bit before the next receive  
occurred, the ACK is not sent and the SSP-  
BUF is updated.  
When the address byte overflow condition exists, then  
no acknowledge (ACK) pulse is given. An overflow con-  
dition is defined as either bit BF (SSPSTAT<0>) is set  
or bit SSPOV (SSPCON<6>) is set.  
TABLE 9-2  
DATA TRANSFER RECEIVED BYTE ACTIONS  
Status Bits as Data  
Transfer is Received  
Set bit SSPIF  
Generate ACK  
Pulse  
(SSP Interrupt occurs  
if enabled)  
BF  
SSPOV  
SSPSR SSPBUF  
0
1
1
0
0
0
1
1
Yes  
No  
Yes  
No  
No  
No  
Yes  
Yes  
Yes  
Ye s  
No  
Yes  
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.  
9.2.1.3  
SLAVE TRANSMISSION  
An SSP interrupt is generated for each data transfer  
byte. The SSPIF flag bit must be cleared in software  
and the SSPSTAT register is used to determine the sta-  
tus of the byte transfer. The SSPIF flag bit is set on the  
falling edge of the ninth clock pulse.  
When the R/W bit of the incoming address byte is set  
and an address match occurs, the R/W bit of the  
SSPSTAT register is set. The received address is  
loaded into the SSPBUF register. The ACK pulse will  
be sent on the ninth bit, and the SCL pin is held low.  
The transmit data must be loaded into the SSPBUF  
register, which also loads the SSPSR register. Then the  
SCL pin should be enabled by setting bit CKP (SSP-  
CON<4>). The master must monitor the SCL pin prior  
to asserting another clock pulse. The slave devices  
may be holding off the master by stretching the clock.  
The eight data bits are shifted out on the falling edge of  
the SCL input. This ensures that the SDA signal is valid  
during the SCL high time (Figure 9-7).  
As a slave-transmitter, the ACK pulse from the master  
receiver is latched on the rising edge of the ninth SCL  
input pulse. If the SDA line is high (not ACK), then the  
data transfer is complete. When the not ACK is latched  
by the slave, the slave logic is reset and the slave then  
monitors for another occurrence of the START bit. If the  
SDA line was low (ACK), the transmit data must be  
loaded into the SSPBUF register, which also loads the  
SSPSR register. Then the SCL pin should be enabled  
by setting the CKP bit.  
2
FIGURE 9-6: I C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)  
R/W=0  
ACK  
Not  
Receiving Address  
A7 A6 A5 A4  
Receiving Data  
Receiving Data  
ACK  
ACK  
D5  
D2  
6
D0  
8
D5  
D2  
D0  
8
SDA  
A3 A2 A1  
D7 D6  
D4 D3  
D7 D6  
D4 D3  
D1  
7
D1  
7
3
9
5
4
7
1
2
4
9
3
6
9
5
1
2
3
6
1
2
4
8
5
P
SCL  
S
SSPIF  
Bus Master  
terminates  
transfer  
BF (SSPSTAT<0>)  
Cleared in software  
SSPBUF register is read  
SSPOV (SSPCON<6>)  
Bit SSPOV is set because the SSPBUF register is still full.  
ACK is not sent.  
1999 Microchip Technology Inc.  
DS30292B-page 73  
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