PIC16F87X
9.2.5
MASTER MODE
In master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the MSSP module is dis-
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt if enabled):
• START condition
2
abled. Control of the I C bus may be TACKEN when the
• STOP condition
P bit is set, or the bus is idle with both the S and P bits
clear.
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
2
FIGURE 9-9: SSP BLOCK DIAGRAM (I C MASTER MODE)
Internal
Data Bus
SSPM3:SSPM0,
SSPADD<6:0>
Read
Write
SSPBUF
SSPSR
Baud
Rate
Generator
Shift
Clock
SDA
SDA in
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate
SCL
Start bit detect,
Stop bit detect
Write collision detect
Clock Arbitration
State counter for
end of XMIT/RCV
SCL in
Bus Collision
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
DS30292B-page 76
1999 Microchip Technology Inc.
ETC [ ETC ]
