PIC12F510/16F506
TABLE 11-2: INSTRUCTION SET SUMMARY
12-Bit Opcode
MSb LSb
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
1
1
1
1
1
0001 11df ffff C, DC, Z 1, 2, 4
0001 01df ffff
0000 011f ffff
0000 0100 0000
0010 01df ffff
0000 11df ffff
0010 11df ffff
0010 10df ffff
0011 11df ffff
0001 00df ffff
0010 00df ffff
0000 001f ffff
0000 0000 0000
0011 01df ffff
0011 00df ffff
Z
Z
Z
Z
Z
None
Z
None
Z
2, 4
4
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1
2, 4
2, 4
2, 4
2, 4
2, 4
2, 4
1, 4
DECFSZ
INCF
1(2)
1
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
1(2)
1
1
1
1
1
1
1
1
1
Z
None
None
C
–
f, d
f, d
f, d
f, d
f, d
2, 4
2, 4
C
0000 10df ffff C, DC, Z 1, 2, 4
0011 10df ffff
0001 10df ffff
None
Z
2, 4
2, 4
Exclusive OR W with f
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
0100 bbbf ffff
None
None
None
None
2, 4
2, 4
0101 bbbf ffff
0110 bbbf ffff
0111 bbbf ffff
1(2)
1(2)
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
k
k
–
k
k
k
–
k
–
f
AND literal with W
Call Subroutine
1
2
1
2
1
1
1
2
1
1
1
1110 kkkk kkkk
1001 kkkk kkkk
0000 0000 0100 TO, PD
101k kkkk kkkk
1101 kkkk kkkk
1100 kkkk kkkk
0000 0000 0010
1000 kkkk kkkk
Z
None
1
3
Clear Watchdog Timer
Unconditional branch
Inclusive OR literal with W
Move literal to W
Load OPTION register
Return, place literal in W
Go into Standby mode
Load TRIS register
None
Z
None
None
None
0000 0000 0011 TO, PD
0000 0000 0fff
1111 kkkk kkkk
None
Z
XORLW
k
Exclusive OR literal to W
Note 1: The 9th bit of the Program Counter will be forced to a ‘0’ by any instruction that writes to the PC except for
GOTO. See Section 4.6 “Program Counter”.
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state
latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
DS41268B-page 72
Preliminary
© 2006 Microchip Technology Inc.
ETC [ ETC ]
