PIC12F510/16F506
ADDWF
Add W and f
BCF
Bit Clear f
Syntax:
[ label ] ADDWF f,d
Syntax:
[ label ] BCF f,b
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Operation:
(W) + (f) → (dest)
Operation:
0 → (f<b>)
Status
C, DC, Z
Status Affected: None
Affected:
Description:
Bit ‘b’ in register ‘f’ is cleared.
Description:
Add the contents of the W register
and register ‘f’. If ‘d’ is ‘0’, the result
is stored in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
ANDLW
AND literal with W
BSF
Bit Set f
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] BSF f,b
Operands:
Operation:
Status Affected:
Description:
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
(W).AND. (k) → (W)
Operation:
1 → (f<b>)
Z
Status Affected: None
The contents of the W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
Description:
Bit ‘b’ in register ‘f’ is set.
ANDWF
AND W with f
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] ANDWF f,d
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Operation:
(W) .AND. (f) → (dest)
Operation:
skip if (f<b>) = 0
Status Affected: Z
Status Affected: None
Description: The contents of the W register are
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W regis-
ter. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
next instruction is skipped.
If bit ‘b’ is ‘0’, then the next instruc-
tion fetched during the current
instruction execution is discarded,
and a NOPis executed instead,
making this a two-cycle instruction.
© 2006 Microchip Technology Inc.
Preliminary
DS41268B-page 73
ETC [ ETC ]
