PIC12F510/16F506
BTFSS
Bit Test f, Skip if Set
CLRW
Clear W
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRW
Operands:
0 ≤ f ≤ 31
0 ≤ b < 7
Operands:
Operation:
None
00h → (W);
1 → Z
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected:
Description:
Z
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the
The W register is cleared. Zero bit
(Z) is set.
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOPis executed instead,
making this a two-cycle instruction.
CALL
Subroutine Call
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
0 ≤ k ≤ 255
Syntax:
[ label ] CLRWDT
Operands:
Operation:
Operands:
Operation:
None
(PC) + 1→ Top-of-Stack;
k → PC<7:0>;
00h → WDT;
0 → WDT prescaler (if assigned);
(STATUS <6:5>) → PC<10:9>;
0 → PC<8>
1 → TO;
1 → PD
Status Affected: None
Status Affected: TO, PD
Description:
Subroutine call. First, return
Description:
The CLRWDTinstruction resets the
address (PC + 1) is PUSHed onto
the stack. The eight-bit immediate
address is loaded into PC
WDT. It also resets the prescaler,
if the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
bits <7:0>. The upper bits
PC<10:9> are loaded from
STATUS <6:5>, PC<8> is cleared.
CALLis a two-cycle instruction.
CLRF
Clear f
COMF
Complement f
Syntax:
[ label ] CLRF
0 ≤ f ≤ 31
f
Syntax:
[ label ] COMF f,d
Operands:
Operation:
Operands:
0 ≤ f ≤ 31
d ∈ [0,1]
00h → (f);
1 → Z
Operation:
(f) → (dest)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ‘f’ are
cleared and the Z bit is set.
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
DS41268B-page 74
Preliminary
© 2006 Microchip Technology Inc.
ETC [ ETC ]
