PIC12F510/16F506
FIGURE 10-8:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
VDD
Power-up
Detect
POR (Power-on Reset)
MCLR Reset
(GP3/RB3)/MCLR/VPP
S
R
Q
Q
MCLRE
WDT Reset
Start-up Timer
WDT Time-out
CHIP Reset
(10 ms, 1.125 ms
or 18 ms)
Pin Change
Sleep
Wake-up on pin Change Reset
Comparator Change
Wake-up on
Comparator Change
FIGURE 10-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
FIGURE 10-10:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
DS41268B-page 64
Preliminary
© 2006 Microchip Technology Inc.
ETC [ ETC ]
