PIC12F510/16F506
FIGURE 6-2:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC - 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
Instruction
Fetch
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
NT0 + 1
T0
T0 + 1
T0 + 2
NT0
NT0 + 2
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
FIGURE 6-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC - 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Instruction
Fetch
T0
T0 + 1
NT0
NT0 + 1
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Bit 0 Power-On
Reset
Value on
All Other
Resets
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
01h
07h
TMR0
Timer0 – 8-bit Real-Time Clock/Counter
C1OUT C1OUTEN C1POL C1T0CS
C1OUT C1OUTEN C1POL C1T0CS
xxxx xxxx uuuu uuuu
1111 1111 uuuu uuuu
C1NREF C1PREF C1WU
(2)
(3)
CM1CON0
CM1CON0
OPTION
C1ON
C1ON
PSA
08h
N/A
N/A
C1NREF C1PREF C1WU 1111 1111 uuuu uuuu
GPWU
—
GPPU
—
T0CS
T0SE
PS2
PS1
PS0 1111 1111 1111 1111
(1)
TRISGPIO
I/O Control Register
---- 1111 --11 1111
Legend:
Shaded cells not used by Timer0, – = unimplemented, x = unknown, u= unchanged.
Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1.
2: For PIC12F510.
3: For PIC16F506.
DS41268B-page 40
Preliminary
© 2006 Microchip Technology Inc.
ETC [ ETC ]
