TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
15 Test-Pattern Generation/Detection Registers (continued)
Table 520. TPG_CONFIG2, Register (R/W)
Address
Bit
Name
Function
Reset
Default
0x60032 15:13
TPM_SEQ2[2:0]
TPM_TPINV2
TPG_TPINV2
TPM_EDGE2
These bits select the test pattern to be monitored by the
tpg on the E1 test input.
000
0
12
11
10
This bit, if set, inverts the received data for E1 test sig-
nals.
This bit, if set, inverts the transmitted data for E1 test sig-
nals.
0
This bit, if set, selects the rising edge of XC_TCLK[2] for
use as the retiming clock edge, or else selects falling
edge.
1
9
8
TPG_EDGE2
This bit, if set, selects the rising edge of TPG_CLK[2] for
use as the transmit clock edge, or else selects falling
edge.
1
0
TPG_TPM_CRC4_EN2 This bit, if set, enables CRC-4 insertion if E1 framing is
selected.
This bit is common to the generator and monitor sides.
7:6 TPG_TPM_CODE2[1:0] Do not use line coding/decoding when 00.
00
Use HDB3 coding/decoding when 01.
Use B8ZS coding/decoding when 10.
Use AMI coding/decoding when 11.
This code is common to the generator and monitor sides.
5
4
TPM_FRAME2
TPG_FINV2
This bit is set to select a framed E1 test pattern.
0
0
If this bit is set, the frame alignment sequence (normally
0011011) is transmitted with the last bit inverted
(0011010).
3
TPG_FRAME2
TPG_SEQ2[2:0]
This bit is set to select a framed E1 test pattern.
0
2:0
These bits select the test pattern to be generated and
transmitted by the TPG on the E1 test output
(TPG_DATA[2]).
000
000 = PRBS15.
001 = PRBS20.
010 = QRSS.
011 = PRBS23.
100 = alternating 01.
101 = all ones.
110 = unused.
111 = user defined.
352
Agere Systems Inc.
ETC [ ETC ]
