TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
15 Test-Pattern Generation/Detection Registers (continued)
Table 509. TPG_VAL_OOS, Register (RO)
Address Bit
Name
Function
Reset
Default
0x60021 15:6
5
RSVD
Reserved.
0x000
1
TPM_OOS5
This status bit is set whenever the TPM DS3 test monitor has
encountered an out of sync condition.
4
TPM_OOS4
This status bit is set whenever the TPM DS2 test monitor has
encountered an out of sync condition.
1
3
2
RSVD
Reserved.
0
1
TPM_OOS2
This status bit is set whenever the TPM E1 test monitor has
encountered an out of sync condition.
1
0
RSVD
Reserved.
0
1
TPM_OOS0
This status bit is set whenever the TPM DS1 test monitor has
encountered an out of sync condition.
Table 510. TPG_VAL_AIS, Register (RO)
Address Bit
Name
Function
Reset
Default
0x60022 15:6
5
RSVD
Reserved.
0x000
0
TPM_AIS5
This status bit is set whenever the TPM DS3 test monitor has
encountered an AIS condition.
4
TPM_AIS4
This status bit is set whenever the TPM DS2 test monitor has
encountered an AIS condition.
0
3
2
RSVD
Reserved.
0
0
TPM_AIS2
This status bit is set whenever the TPM E1 test monitor has
encountered an AIS condition.
1
0
RSVD
Reserved.
0
0
TPM_AIS0
This status bit is set whenever the TPM DS1 test monitor has
encountered an AIS condition.
Table 511. TPG_VAL_FER, Register (RO)
Address Bit
Name
Function
Reset
Default
0x60023 15:3
2
RSVD
Reserved.
0x0000
0
TPM_FER2
This status bit is set whenever the TPM E1 test monitor has
encountered an FER condition.
1
0
RSVD
Reserved.
0
0
TPM_FER0
This status bit is set whenever the TPM DS1 test monitor has
encountered an FER condition.
348
Agere Systems Inc.
ETC [ ETC ]
