Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
15 Test-Pattern Generation/Detection Registers (continued)
Table 512. TPG_VAL_CRCE, Register (RO)
Address Bit
Name
Function
Reset
Default
0x60024 15:3
2
RSVD
Reserved.
0x0000
0
TPG_CRCEINS2 This bit is set when the user desires to inject a single CRC error
into the E1 test signal (via 0 to 1 transition).
1
0
RSVD
Reserved.
0
0
TPG_CRCEINS0 This bit is set when the user desires to inject a single CRC error
Into the DS1 test signal (via 0 to 1 transition).
Table 513. TPG_BER_INSRT, Register (R/W)
Address Bit Name
Function
Reset
Default
0x60028
15
TPG_BER_EN This bit, when set, allows automatic bit error insertion by the
microprocessor.
0
14:6
5
RSVD
Reserved.
0x000
0
TPG_BERINS5 This bit is set when the user desires to inject a single bit error into
the DS3 test signal via SMPR_BER_INSRT (Table 75 on
page 68).
4
TPG_BERINS4 This bit is set when the user desires to inject a single bit error into
the DS2 test signal via SMPR_BER_INSRT.
0
3
2
RSVD
Reserved.
0
0
TPG_BERINS2 This bit is set when the user desires to inject a single bit error into
the E1 test signal via SMPR_BER_INSRT.
1
0
RSVD
Reserved.
0
0
TPG_BERINS0 This bit is set when the user desires to inject a single bit error into
the DS1 test signal via SMPR_BER_INSRT.
Table 514. TPG_FER_INSRT, Register (R/W)
Address Bit
Name
Function
Reset
Default
0x60029 15:3
2
RSVD
Reserved.
0x0000
0
TPG_FERINS2 This bit injects a single framing error into the E1 test signal (via 0
to 1 transition).
1
0
RSVD
Reserved.
0
0
TPG_FERINS0 This bit injects a single framing error into the DS1 test signal (via
0 to 1 transition).
Table 515. TPG_CRCE_INSRT, Register (R/W)
Address Bit
Name
Function
Reset
Default
0x6002A 15:3
2
RSVD
Reserved.
0x0000
0
TPG_CRC4EINS2 This bit is set when the user desires to inject a single
CRC-4 error into the E1 test signal (via 0 to 1 transition).
1
0
RSVD
Reserved.
0
0
TPG_CRC6EINS0 This bit is set when the user desires to inject a single
CRC-6 error into the DS1 test signal (via 0 to 1 transition).
Agere Systems Inc.
349
ETC [ ETC ]
