TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Data Sheet
June 2002
15 Test-Pattern Generation/Detection Registers (continued)
Table 522. TPG_CONFIG5, Register (R/W)
Address
Bit
Name
Function
Reset
Default
0x60035 15:13 TPM_SEQ5[2:0] These bits select the test pattern to be monitored by the TPG on
the DS3 test input.
000
12
11
10
TPM_TPINV5
TPG_TPINV5
TPM_EDGE5
This bit, if set, inverts the received data for DS3 test signals.
This bit, if set, inverts the transmitted data for DS3 test signals.
0
0
1
This bit, if set, selects the rising edge of XC_TCLK[5] for use as
the retiming clock edge, or else selects falling edge.
9
TPG_EDGE5
RSVD
This bit, if set, selects the rising edge of TPG_CLK[5] for use as
the transmit clock edge, or else selects falling edge.
1
8:3
2:0
Reserved.
—
0
TPG_SEQ5[2:0] These bits select the test pattern to be generated and transmitted
by the TPG on the DS3 output (TPG_DATA[5]).
000 = PRBS15.
001 = PRBS20.
010 = QRSS.
011 = PRBS23.
100 = alternating 01.
101 = all ones.
110 = unused.
111 = user defined.
Table 523. TPG_USER, Register (R/W)
Address Bit Name
Function
Reset
Default
0x60036 15:0 TPG_USER[15:0] User-Programmed Test Pattern Generator Data.
0xDEAD
Table 524. TPM_USER, Register (R/W)
Address
Bit
Name
Function
Reset
Default
0x60037 15:0 TPM_USER[15:0] User-Programmed Test Pattern Monitor Data.
0xBEEF
Table 525. TPG_BERCNT0, Register (RO)
Address
Bit
Name
Function
Reset
Default
0x60040 15:0 TPM_CNT0[15:0] This field holds the current counter value for DS1 test pattern bit 0x0000
errors as detected by the TPM.
354
Agere Systems Inc.