Data Sheet
June 2002
TMXF28155 Supermapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
15 Test-Pattern Generation/Detection Registers (continued)
Table 521. TPG_CONFIG4, Register (R/W)
Address
Bit
Name
Function
Reset
Default
0x60034 15:13 TPM_SEQ4[2:0] These bits select the test pattern to be monitored by the TPG on
the DS2 test input.
000
12
11
10
TPM_TPINV4
TPG_TPINV4
TPM_EDGE4
This bit, if set, inverts the received data for DS2 test signals.
This bit, if set, inverts the transmitted data for DS2 test signals.
0
0
1
This bit, if set, selects the rising edge of XC_TCLK[4] for use as
the retiming clock edge, or else selects falling edge.
9
TPG_EDGE4
RSVD
This bit, if set, selects the rising edge of TPG_CLK[4] for use as
the transmit clock edge, or else selects falling edge.
1
8:3
2:0
Reserved.
—
0
TPG_SEQ4[2:0] These bits select the test pattern to be generated and transmit-
ted by the TPG on the DS2 output (TPG_DATA[4]).
000 = PRBS15.
001 = PRBS20.
010 = QRSS.
011 = PRBS23.
100 = alternating 01.
101 = all ones.
110 = unused.
111 = user defined.
Agere Systems Inc.
353
ETC [ ETC ]
